A. Cook, S. Hellebrand, M. E. Imhof, A. Mumtaz, and H.-J. Wunderlich, “Built-in Self-Diagnosis Targeting Arbitrary Defects with Partial Pseudo-Exhaustive Test,” in 13th IEEE Latin American Test Workshop (LATW’12), 2012, pp. 1–4.
LibreCat: /record/12980
DOI: 10.1109/latw.2012.6261229

A. Cook, S. Hellebrand, and H.-J. Wunderlich, “Built-in Self-Diagnosis Exploiting Strong Diagnostic Windows in Mixed-Mode Test,” in 17th IEEE European Test Symposium (ETS’12), 2012, pp. 1–6.
LibreCat: /record/12981
DOI: 10.1109/ets.2012.6233025

A. Cook, S. Hellebrand, and H.-J. Wunderlich, Eingebaute Selbstdiagnose mit zufälligen und deterministischen Mustern. 24. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’12), Cottbus, Germany, 2012.
LibreCat: /record/13074

A. Cook, S. Hellebrand, T. Indlekofer, and H.-J. Wunderlich, “Diagnostic Test of Robust Circuits,” in 20th IEEE Asian Test Symposium (ATS’11), 2011, pp. 285–290.
LibreCat: /record/12982
DOI: 10.1109/ats.2011.55

I. Polian, B. Becker, S. Hellebrand, H.-J. Wunderlich, and P. Maxwell, “Towards Variation-Aware Test Methods,” in 16th IEEE European Test Symposium Trondheim (ETS’11), 2011.
LibreCat: /record/12984
DOI: 10.1109/ets.2011.51

A. Cook, S. Hellebrand, T. Indlekofer, and H.-J. Wunderlich, “Robuster Selbsttest mit Diagnose,” in 5. GMM/GI/ITG Fachtagung “Zuverlässigkeit und Entwurf,” 2011, pp. 48–53.
LibreCat: /record/13053

F. Hopsch et al., “Variation-Aware Fault Modeling,” SCIENCE CHINA Information Sciences, Science China Press, co-published with Springer, vol. 54, no. 4, pp. 1813–1826, 2011.
LibreCat: /record/13052

A. Kamran, N. Nemati, S. Sadeghi-Kohan, and Z. Navabi, “Virtual tester development using HDL/PLI,”10.1109/ewdts.2010.5742156__2011, doi:10.1109/ewdts.2010.5742156 .
LibreCat: /record/46272
DOI: 10.1109/ewdts.2010.5742156

V. Fröse, R. Ibers, and S. Hellebrand, Testdatenkompression mit Hilfe der Netzwerkinfrastruktur. 22. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’10), Paderborn, Germany, 2010.
LibreCat: /record/10670

B. Becker, S. Hellebrand, I. Polian, B. Straube, W. Vermeiren, and H.-J. Wunderlich, “Massive Statistical Process Variations - A Grand Challenge for Testing Nanoelectronic Circuits,” in 40th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W’10), 2010.
LibreCat: /record/12987
DOI: 10.1109/dsnw.2010.5542612

M. Hunger and S. Hellebrand, “Ausbeute und Fehlertoleranz bei dreifach modularer Redundanz,” in 4. GMM/GI/ITG-Fachtagung “Zuverlässigkeit und Entwurf,” 2010, pp. 81–88.
LibreCat: /record/13051

S. Hellebrand, Nano-Electronic Systems. Editorial, it 4/2010, pp. 179-180, 2010.
LibreCat: /record/13073

F. Hopsch et al., “Variation-Aware Fault Modeling,”10.1109/ats.2010.24__in 19th IEEE Asian Test Symposium (ATS’10), 2010, pp. 87–93, doi:10.1109/ats.2010.24 .
LibreCat: /record/12983
DOI: 10.1109/ats.2010.24

T. Indlekofer, M. Schnittger, and S. Hellebrand, “Efficient Test Response Compaction for Robust BIST Using Parity Sequences,”10.1109/iccd.2010.5647648__in 28th IEEE International Conference on Computer Design (ICCD’10), 2010, pp. 480–485, doi:10.1109/iccd.2010.5647648 .
LibreCat: /record/12985
DOI: 10.1109/iccd.2010.5647648

M. Hunger and S. Hellebrand, “The Impact of Manufacturing Defects on the Fault Tolerance of TMR-Systems,”10.1109/dft.2010.19__in 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’10), 2010, pp. 101–108, doi:10.1109/dft.2010.19 .
LibreCat: /record/12986
DOI: 10.1109/dft.2010.19

V. Froese, R. Ibers, and S. Hellebrand, “Reusing NoC-Infrastructure for Test Data Compression,”10.1109/vts.2010.5469570__in 28th IEEE VLSI Test Symposium (VTS’10), 2010, pp. 227–231, doi:10.1109/vts.2010.5469570 .
LibreCat: /record/12988
DOI: 10.1109/vts.2010.5469570

B. Becker, S. Hellebrand, I. Polian, B. Straube, W. Vermeiren, and H.-J. Wunderlich, “Massive Statistical Process Variations - A Grand Challenge for Testing Nanoelectronic Circuits,” 2010.
LibreCat: /record/13049

T. Indlekofer, M. Schnittger, and S. Hellebrand, “Robuster Selbsttest mit extremer Kompaktierung,” in 4. GMM/GI/ITG-Fachtagung “Zuverlässigkeit und Entwurf,” 2010, pp. 17–24.
LibreCat: /record/13050

M. Hunger, S. Hellebrand, A. Czutro, I. Polian, and B. Becker, “ATPG-Based Grading of Strong Fault-Secureness,”10.1109/iolts.2009.5196027__2009, doi:10.1109/iolts.2009.5196027 .
LibreCat: /record/12991
DOI: 10.1109/iolts.2009.5196027

S. Hellebrand and M. Hunger, “Are Robust Circuits Really Robust?,”10.1109/dft.2009.28__in 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’09), (Invited Talk), 2009, p. 77, doi:10.1109/dft.2009.28 .
LibreCat: /record/12990
DOI: 10.1109/dft.2009.28

M. Hunger, S. Hellebrand, A. Czutro, I. Polian, and B. Becker, “Robustheitsanalyse stark fehlersicherer Schaltungen mit SAT-basierter Testmustererzeugung,” 2009.
LibreCat: /record/13030

T. Coym, S. Hellebrand, S. Ludwig, B. Straube, H.-J. Wunderlich, and C. G. Zoellin, Ein verfeinertes elektrisches Modell für Teilchentreffer und dessen Auswirkung auf die Bewertung der Schaltungsempfindlichkeit. 20. ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (Poster), Wien, Österreich, 2008.
LibreCat: /record/13033

U. Amgalan, C. Hachmann, S. Hellebrand, and H.-J. Wunderlich, Testen mit Rücksetzpunkten - ein Ansatz zur Verbesserung der Ausbeute bei robusten Schaltungen. 20. ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Wien, Österreich, 2008.
LibreCat: /record/13035

P. Oehler, A. Bosio, G. di Natale, and S. Hellebrand, “A Modular Memory BIST for Optimized Memory Repair,”10.1109/iolts.2008.30__2008, doi:10.1109/iolts.2008.30 .
LibreCat: /record/12992
DOI: 10.1109/iolts.2008.30

U. Amgalan, C. Hachmann, S. Hellebrand, and H.-J. Wunderlich, “Signature Rollback - A Technique for Testing Robust Circuits,”10.1109/vts.2008.34__in 26th IEEE VLSI Test Symposium (VTS’08), 2008, pp. 125–130, doi:10.1109/vts.2008.34 .
LibreCat: /record/12994
DOI: 10.1109/vts.2008.34

M. Hunger and S. Hellebrand, “Verification and Analysis of Self-Checking Properties through ATPG,”10.1109/iolts.2008.32__2008, doi:10.1109/iolts.2008.32 .
LibreCat: /record/12993
DOI: 10.1109/iolts.2008.32

M. Hunger and S. Hellebrand, “Analyse selbstprüfender Schaltungen – Nachweis von Fehlersicherheit und Selbsttestbarkeit mit ATPG,” 2008.
LibreCat: /record/13031

P. Oehler, A. Bosio, G. Di Natale, and S. Hellebrand, “Modularer Selbsttest und optimierte Reparaturanalyse,” 2008.
LibreCat: /record/13032

S. Hellebrand, Reliable Nanoscale Systems - Challenges and Strategies for On- and Offline Testing. 5th IEEE East-West Design \'26; Test Symposium, Yerevan, Armenia (Invited Talk), 2007.
LibreCat: /record/13038

M. Ali, M. Welzl, S. Hessler, and S. Hellebrand, An End-to-End Reliability Protocol to Address Transient Faults in Network on Chips. DATE 2007 Friday Workshop on Diagnostic Services in Network-on-Chips, Nice, France, (Poster), 2007.
LibreCat: /record/13039

P. Oehler, S. Hellebrand, and H.-J. Wunderlich, An Integrated Built-in Test and Repair Approach for Memories with 2D Redundancy. 17th GI/ITG/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Erlangen, Germany, 2007.
LibreCat: /record/13042

S. Hellebrand, Qualitätssicherung für Nanochips - Wie IT-Produkte zuverlässig werden. ForschungsForum Paderborn, 10. Ausgabe, Paderborn, Germany, 2007.
LibreCat: /record/13043

S. Hellebrand, C. G. Zoellin, H.-J. Wunderlich, S. Ludwig, T. Coym, and B. Straube, “A Refined Electrical Model for Particle Strikes and its Impact on SEU Prediction,”10.1109/dft.2007.43__in 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT’07), 2007, pp. 50–58, doi:10.1109/dft.2007.43 .
LibreCat: /record/12995
DOI: 10.1109/dft.2007.43

P. Oehler, S. Hellebrand, and H.-J. Wunderlich, “Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test and Repair,”10.1109/ddecs.2007.4295278__in 10th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS’07), 2007, pp. 185–190, doi:10.1109/ddecs.2007.4295278 .
LibreCat: /record/12996
DOI: 10.1109/ddecs.2007.4295278

P. Oehler, S. Hellebrand, and H.-J. Wunderlich, “An Integrated Built-In Test and Repair Approach for Memories with 2D Redundancy,”10.1109/ets.2007.10__in 12th IEEE European Test Symposium (ETS’07), 2007, pp. 91–96, doi:10.1109/ets.2007.10 .
LibreCat: /record/12997
DOI: 10.1109/ets.2007.10

S. Hellebrand, C. G. Zoellin, H.-J. Wunderlich, S. Ludwig, T. Coym, and B. Straube, “Testing and Monitoring Nanoscale Systems - Challenges and Strategies for Advanced Quality Assurance,” 2007.
LibreCat: /record/13037

S. Hellebrand, C. G. Zoellin, H.-J. Wunderlich, S. Ludwig, T. Coym, and B. Straube, “Testing and Monitoring Nanoscale Systems - Challenges and Strategies for Advanced Quality Assurance,” Informacije MIDEM, Ljubljana (Invited Paper), vol. 37, no. 4 (124), pp. 212–219, 2007.
LibreCat: /record/13036

M. Ali, S. Hessler, M. Welzl, and S. Hellebrand, “An Efficient Fault Tolerant Mechanism to Deal with Permanent and Transient Failures in a Network on Chip,” International Journal on High Performance Systems Architecture, vol. 1, no. 2, pp. 113–123, 2007.
LibreCat: /record/13044

M. Ali, M. Welzl, S. Hessler, and S. Hellebrand, “A Fault Tolerant Mechanism for Handling Permanent and Transient Failures in a Network on Chip,” in 4th International Conference on Information Technology: New Generations (ITNG’07), 2007, pp. 1027–1032.
LibreCat: /record/13040

B. Becker, I. Polian, S. Hellebrand, B. Straube, and H.-J. Wunderlich, “Test und Zuverlässigkeit nanoelektronischer Systeme,” 2007.
LibreCat: /record/13041

B. Becker, I. Polian, S. Hellebrand, B. Straube, and H.-J. Wunderlich, “DFG-Projekt RealTest - Test und Zuverlässigkeit nanoelektronischer Systeme,” it - Information Technology, vol. 48, no. 5, pp. 305–311, 2006.
LibreCat: /record/13045

P. Oehler and S. Hellebrand, A Low Power Design for Embedded DRAMs with Online Consistency Checking. Kleinheubachertagung 2005, Miltenberg, Germany, 2005.
LibreCat: /record/13046

M. Ali, M. Welzl, and S. Hellebrand, Dynamic Routing: A Prerequisite for Reliable NoCs. 17th GI/ITG/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Innsbruck, Austria, 2005.
LibreCat: /record/13101

P. Oehler and S. Hellebrand, Power Consumption Versus Error Correcting Capabilities in Embedded DRAMs - A Case Study. 17th GI/ITG/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Innsbruck, Austria, 2005.
LibreCat: /record/13102

M. Ali, M. Welzl, M. Zwicknagl, and S. Hellebrand, “Considerations for Fault-Tolerant Networks on Chips,”10.1109/icm.2005.1590063__2005, doi:10.1109/icm.2005.1590063 .
LibreCat: /record/12999
DOI: 10.1109/icm.2005.1590063

P. Oehler and S. Hellebrand, “Low Power Embedded DRAMs with High Quality Error Correcting Capabilities,”10.1109/ets.2005.28__in 10th IEEE European Test Symposium (ETS’05), 2005, pp. 148–153, doi:10.1109/ets.2005.28 .
LibreCat: /record/13000
DOI: 10.1109/ets.2005.28

M. Ali, M. Welzl, and S. Hellebrand, “A Dynamic Routing Mechanism for Network on Chip,”10.1109/norchp.2005.1596991__in 23rd IEEE NORCHIP Conference, 2005, pp. 70–73, doi:10.1109/norchp.2005.1596991 .
LibreCat: /record/12998
DOI: 10.1109/norchp.2005.1596991

M. Liu Jing et al., “Sensor Networks with More Features Using Less Hardware,” in GOR/NGB Conference Tilburg 2004, 2004.
LibreCat: /record/13071

R. Breu, T. Fahringer, D. Fensel, S. Hellebrand, A. Middeldorp, and O. Scherzer, Im Westen viel Neues - Informatik an der Universität Innsbruck. OCG Journal, pp. 28-29, 2004.
LibreCat: /record/13099

S. Hellebrand, A. Wuertenberger, and C. S. Tautermann, Data Compression for Multiple Scan Chains Using Dictionaries with Corrections. 9th IEEE European Test Symposium, Ajaccio, Corsica, France, 2004.
LibreCat: /record/13100