Oehler, Philipp, et al. An Integrated Built-in Test and Repair Approach for Memories with 2D Redundancy. 2007.
LibreCat: /record/13042

Hellebrand, Sybille. Qualitätssicherung Für Nanochips - Wie IT-Produkte Zuverlässig Werden. 2007.
LibreCat: /record/13043

Hellebrand, Sybille, et al. “A Refined Electrical Model for Particle Strikes and Its Impact on SEU Prediction.”10.1109/dft.2007.43__22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT’07), IEEE, 2007, pp. 50–58, doi:10.1109/dft.2007.43.
LibreCat: /record/12995
DOI: 10.1109/dft.2007.43

Oehler, Philipp, et al. “Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test and Repair.”10.1109/ddecs.2007.4295278__10th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS’07), IEEE, 2007, pp. 185–90, doi:10.1109/ddecs.2007.4295278.
LibreCat: /record/12996
DOI: 10.1109/ddecs.2007.4295278

Oehler, Philipp, et al. “An Integrated Built-In Test and Repair Approach for Memories with 2D Redundancy.”10.1109/ets.2007.10__12th IEEE European Test Symposium (ETS’07), IEEE, 2007, pp. 91–96, doi:10.1109/ets.2007.10.
LibreCat: /record/12997
DOI: 10.1109/ets.2007.10

Hellebrand, Sybille, et al. “Testing and Monitoring Nanoscale Systems - Challenges and Strategies for Advanced Quality Assurance.” 43rd International Conference on Microelectronics, Devices and Material with the Workshop on Electronic Testing (MIDEM’07), (Invited Paper), 2007.
LibreCat: /record/13037

Hellebrand, Sybille, et al. “Testing and Monitoring Nanoscale Systems - Challenges and Strategies for Advanced Quality Assurance.” Informacije MIDEM, Ljubljana (Invited Paper), vol. 37, no. 4 (124), 2007, pp. 212–19.
LibreCat: /record/13036

Ali, Muhammad, et al. “An Efficient Fault Tolerant Mechanism to Deal with Permanent and Transient Failures in a Network on Chip.” International Journal on High Performance Systems Architecture, vol. 1, no. 2, 2007, pp. 113–23.
LibreCat: /record/13044

Ali, Muhammad, et al. “A Fault Tolerant Mechanism for Handling Permanent and Transient Failures in a Network on Chip.” 4th International Conference on Information Technology: New Generations (ITNG’07), 2007, pp. 1027–32.
LibreCat: /record/13040

Becker, Bernd, et al. “Test Und Zuverlässigkeit Nanoelektronischer Systeme.” 1. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf,” 2007.
LibreCat: /record/13041

Becker, Bernd, et al. “DFG-Projekt RealTest - Test Und Zuverlässigkeit Nanoelektronischer Systeme.” It - Information Technology, vol. 48, no. 5, 2006, pp. 305–11.
LibreCat: /record/13045

Oehler, Philipp, and Sybille Hellebrand. A Low Power Design for Embedded DRAMs with Online Consistency Checking. 2005.
LibreCat: /record/13046

Ali, Muhammad, et al. Dynamic Routing: A Prerequisite for Reliable NoCs. 2005.
LibreCat: /record/13101

Oehler, Philipp, and Sybille Hellebrand. Power Consumption Versus Error Correcting Capabilities in Embedded DRAMs - A Case Study. 2005.
LibreCat: /record/13102

Ali, Muhammad, et al. “Considerations for Fault-Tolerant Networks on Chips.”10.1109/icm.2005.1590063__IEEE International Conference on Microelectronics (ICM’05), IEEE, 2005, doi:10.1109/icm.2005.1590063.
LibreCat: /record/12999
DOI: 10.1109/icm.2005.1590063

Oehler, Philipp, and Sybille Hellebrand. “Low Power Embedded DRAMs with High Quality Error Correcting Capabilities.”10.1109/ets.2005.28__10th IEEE European Test Symposium (ETS’05), IEEE, 2005, pp. 148–53, doi:10.1109/ets.2005.28.
LibreCat: /record/13000
DOI: 10.1109/ets.2005.28

Ali, Muhammad, et al. “A Dynamic Routing Mechanism for Network on Chip.”10.1109/norchp.2005.1596991__23rd IEEE NORCHIP Conference, IEEE, 2005, pp. 70–73, doi:10.1109/norchp.2005.1596991.
LibreCat: /record/12998
DOI: 10.1109/norchp.2005.1596991

Liu Jing, Michelle, et al. “Sensor Networks with More Features Using Less Hardware.” GOR/NGB Conference Tilburg 2004, 2004.
LibreCat: /record/13071

Breu, Ruth, et al. Im Westen Viel Neues - Informatik an Der Universität Innsbruck. 2004.
LibreCat: /record/13099

Hellebrand, Sybille, et al. Data Compression for Multiple Scan Chains Using Dictionaries with Corrections. 2004.
LibreCat: /record/13100

Wuertenberger, Armin, et al. “Data Compression for Multiple Scan Chains Using Dictionaries with Corrections.”10.1109/test.2004.1387357__IEEE International Test Conference (ITC’04), IEEE, 2004, pp. 926–35, doi:10.1109/test.2004.1387357.
LibreCat: /record/13001
DOI: 10.1109/test.2004.1387357

Breu, Ruth, et al. Experiences from Teaching Software Development in a Java Environment. 2003.
LibreCat: /record/13098

Wuertenberger, Armin, et al. “A Hybrid Coding Strategy for Optimized Test Data Compression.”10.1109/test.2003.1270870__IEEE International Test Conference (ITC’03), IEEE, 2003, pp. 451–59, doi:10.1109/test.2003.1270870.
LibreCat: /record/13002
DOI: 10.1109/test.2003.1270870

Hellebrand, Sybille, and Armin Wuertenberger. Alternating Run-Length Coding: A Technique for Improved Test Data Compression. 2002.
LibreCat: /record/13097

Hellebrand, Sybille, et al. “Efficient Online and Offline Testing of Embedded DRAMs.”10.1109/tc.2002.1017700__IEEE Transactions on Computers, vol. 51, no. 7, IEEE, 2002, pp. 801–09, doi:10.1109/tc.2002.1017700.
LibreCat: /record/13003
DOI: 10.1109/tc.2002.1017700

Hellebrand, Sybille, et al. “Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST.” Journal of Electronic Testing - Theory and Applications (JETTA), vol. 18, no. 2, 2002, pp. 157–68.
LibreCat: /record/13069

Liang, Huaguo, et al. “A Mixed-Mode BIST Scheme Based on Folding Compression.” Journal on Computer Science and Technology, vol. 17, no. 2, 2002, pp. 203–12.
LibreCat: /record/13070

Liang, Hua-Guo, et al. Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST. 2001.
LibreCat: /record/13096

Liang, Hua-Guo, et al. “Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST.”10.1109/test.2001.966712__IEEE International Test Conference (ITC’01), IEEE, 2001, pp. 894–902, doi:10.1109/test.2001.966712.
LibreCat: /record/13004
DOI: 10.1109/test.2001.966712

Liang, Hua-Guo, et al. “Deterministic BIST Scheme Based on Reseeding of Folding Counters.” Journal of Computer Research and Development, (Jisuanji Yanjiu Yu Fazhan), vol. 38, no. 8, 2001, p. 931.
LibreCat: /record/13047

Hellebrand, Sybille, et al. “A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters.” Journal of Electronic Testing - Theory and Applications (JETTA), vol. 17, no. 3/4, 2001, pp. 341–49.
LibreCat: /record/13068

Hellebrand, Sybille, and Hans-Joachim Wunderlich. Hardwarepraktikum Im Diplomstudiengang Informatik. 2000.
LibreCat: /record/13094

Hellebrand, Sybille, et al. A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters. 2000.
LibreCat: /record/13095

Hellebrand, Sybille, et al. “A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters.”10.1109/test.2000.894274__IEEE International Test Conference (ITC’00), IEEE, 2000, pp. 778–84, doi:10.1109/test.2000.894274.
LibreCat: /record/13005
DOI: 10.1109/test.2000.894274

Hellebrand, Sybille. Selbsttestbare Steuerwerke - Strukturen Und Syntheseverfahren. Verlag Dr. Kovac, Hamburg, 1999.
LibreCat: /record/13065

Hellebrand, Sybille, et al. Exploiting Symmetries to Speed Up Transparent BIST. 1999.
LibreCat: /record/13093

Hellebrand, Sybille, et al. “Error Detecting Refreshment for Embedded DRAMs.”10.1109/vtest.1999.766693__17th IEEE VLSI Test Symposium (VTS’99), IEEE, 1999, pp. 384–90, doi:10.1109/vtest.1999.766693.
LibreCat: /record/13006
DOI: 10.1109/vtest.1999.766693

N. Yarmolik, Vyacheslav, et al. “Transparent Word-Oriented Memory BIST Based on Symmetric March Algorithms.” Third European Dependable Computing Conference (EDCC-3), 1999.
LibreCat: /record/13066

Hellebrand, Sybille, et al. “Symmetric Transparent BIST for RAMs.” Design Automation and Test in Europe (DATE’99), 1999, pp. 702–07.
LibreCat: /record/13067

Hellebrand, Sybille, and Hans-Joachim Wunderlich. Test Und Synthese Schneller Eingebetteter Systeme. 1998.
LibreCat: /record/13029

N. Yarmolik, Vyacheslav, et al. Efficient Consistency Checking for Embedded Memories. 1998.
LibreCat: /record/13091

N. Yarmolik, Vyacheslav, et al. Efficient Consistency Checking for Embedded Memories. 1998.
LibreCat: /record/13092

Hellebrand, Sybille, et al. “Mixed-Mode BIST Using Embedded Processors.” Mixed-Mode BIST Using Embedded Processors, Kluwer Academic Publishers, 1998.
LibreCat: /record/13060

Hellebrand, Sybille, et al. “Mixed-Mode BIST Using Embedded Processors.” Journal of Electronic Testing Theory and Applications - JETTA, vol. 12, no. 1/2, 1998, pp. 127–38.
LibreCat: /record/13061

Hellebrand, Sybille, et al. “Synthesis of Fast On-Line Testable Controllers for Data-Dominated Applications.” IEEE Design and Test, vol. 15, no. 4, IEEE, 1998, pp. 36–41.
LibreCat: /record/13064

Hertwig, Andre, et al. “Fast Self-Recovering Controllers.”10.1109/vtest.1998.670883__16th IEEE VLSI Test Symposium (VTS’98), IEEE, 1998, pp. 296–302, doi:10.1109/vtest.1998.670883.
LibreCat: /record/13007
DOI: 10.1109/vtest.1998.670883

Hellebrand, Sybille, et al. “Self-Adjusting Output Data Compression: An Efficient BIST Technique for RAMs.”10.1109/date.1998.655853__Design Automation and Test in Europe (DATE’98), 1998, pp. 173–79, doi:10.1109/date.1998.655853.
LibreCat: /record/13008
DOI: 10.1109/date.1998.655853

N. Yarmolik, Vyacheslav, et al. “New Transparent RAM BIST Based on Self-Adjusting Output Data Compression.” Design &; Diagnostics of Electronic Circuits &; Systems (DDECS’98), 1998, pp. 27–33.
LibreCat: /record/13063

Tsai, Kun-Han, et al. STARBIST: Scan Autocorrelated Random Pattern Generation. 1997.
LibreCat: /record/13089

Hertwig, Andre, et al. Synthesis of Fast On-Line Testable Controllers for Data-Dominated Applications. 1997.
LibreCat: /record/13090