Hellebrand, Sybille, et al. “FAST-BIST: Faster-than-at-Speed BIST Targeting Hidden Delay Defects.”10.1109/test.2014.7035360__IEEE International Test Conference (ITC’14), IEEE, 2014, doi:10.1109/test.2014.7035360.

Hellebrand, Sybille, and Hans-Joachim Wunderlich. “SAT-Based ATPG beyond Stuck-at Fault Testing.” DeGruyter Journal on Information Technology (It), vol. 56, no. 4, DeGruyter, 2014, pp. 165–72.

Rodriguez Gomez, Laura, et al. “Adaptive Bayesian Diagnosis of Intermittent Faults.” Journal of Electronic Testing - Theory and Applications (JETTA), vol. 30, no. 5, Springer, 2014, pp. 527–40.

Alizadeh, Bijan, et al. “A Scalable Formal Debugging Approach with Auto-Correction Capability Based on Static Slicing and Dynamic Ranking for RTL Datapath Designs.”10.1109/tc.2014.2329687__IEEE Transactions on Computers, Institute of Electrical and Electronics Engineers (IEEE), 2014, pp. 1–1, doi:10.1109/tc.2014.2329687.

Mohammadi, Marzieh, et al. “An Off-Line MDSI Interconnect BIST Incorporated in BS 1149.1.”10.1109/ets.2014.6847847__2014 19th IEEE European Test Symposium (ETS), IEEE, 2014, doi:10.1109/ets.2014.6847847.

Sadeghi-Kohan, Somayeh, et al. “Improving Polynomial Datapath Debugging with HEDs.”10.1109/ets.2014.6847797__2014 19th IEEE European Test Symposium (ETS), IEEE, 2014, doi:10.1109/ets.2014.6847797.

Hellebrand, Sybille. “Analyzing and Quantifying Fault Tolerance Properties.”10.1109/latw.2013.6562662__14th IEEE Latin American Test Workshop - (LATW’13), IEEE, 2013, doi:10.1109/latw.2013.6562662.

Cook, Alejandro, et al. Adaptive Test and Diagnosis of Intermittent Faults. 2013.

Sadeghi-Kohan, Somayeh, et al. “BS 1149.1 Extensions for an Online Interconnect Fault Detection and Recovery.”10.1109/test.2012.6401583__2012 IEEE International Test Conference, IEEE, 2013, doi:10.1109/test.2012.6401583.

Sadeghi-Kohan, Somayeh, et al. “A New Structure for Interconnect Offline Testing.”10.1109/ewdts.2013.6673207__East-West Design &;amp; Test Symposium (EWDTS 2013), IEEE, 2013, doi:10.1109/ewdts.2013.6673207.

Cook, Alejandro, et al. “Built-in Self-Diagnosis Targeting Arbitrary Defects with Partial Pseudo-Exhaustive Test.”10.1109/latw.2012.6261229__13th IEEE Latin American Test Workshop (LATW’12), IEEE, 2012, pp. 1–4, doi:10.1109/latw.2012.6261229.

Cook, Alejandro, et al. “Built-in Self-Diagnosis Exploiting Strong Diagnostic Windows in Mixed-Mode Test.”10.1109/ets.2012.6233025__17th IEEE European Test Symposium (ETS’12), IEEE, 2012, pp. 1–6, doi:10.1109/ets.2012.6233025.

Cook, Alejandro, et al. Eingebaute Selbstdiagnose Mit Zufälligen Und Deterministischen Mustern. 2012.

Cook, Alejandro, et al. “Diagnostic Test of Robust Circuits.”10.1109/ats.2011.55__20th IEEE Asian Test Symposium (ATS’11), IEEE, 2011, pp. 285–90, doi:10.1109/ats.2011.55.

Polian, Ilia, et al. “Towards Variation-Aware Test Methods.”10.1109/ets.2011.51__16th IEEE European Test Symposium Trondheim (ETS’11), IEEE, 2011, doi:10.1109/ets.2011.51.

Cook, Alejandro, et al. “Robuster Selbsttest Mit Diagnose.” 5. GMM/GI/ITG Fachtagung “Zuverlässigkeit Und Entwurf,” 2011, pp. 48–53.

Hopsch, Fabian, et al. “Variation-Aware Fault Modeling.” SCIENCE CHINA Information Sciences, Science China Press, Co-Published with Springer, vol. 54, no. 4, 2011, pp. 1813–26.

Kamran, Arezoo, et al. “Virtual Tester Development Using HDL/PLI.”10.1109/ewdts.2010.5742156__2010 East-West Design &;amp; Test Symposium (EWDTS), IEEE, 2011, doi:10.1109/ewdts.2010.5742156.

Fröse, Viktor, et al. Testdatenkompression Mit Hilfe Der Netzwerkinfrastruktur. 2010.

Becker, Bernd, et al. “Massive Statistical Process Variations - A Grand Challenge for Testing Nanoelectronic Circuits.”10.1109/dsnw.2010.5542612__40th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W’10), IEEE, 2010, doi:10.1109/dsnw.2010.5542612.

Hunger, Marc, and Sybille Hellebrand. “Ausbeute Und Fehlertoleranz Bei Dreifach Modularer Redundanz.” 4. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf,” 2010, pp. 81–88.

Hellebrand, Sybille. Nano-Electronic Systems. 2010.

Hopsch, Fabian, et al. “Variation-Aware Fault Modeling.”10.1109/ats.2010.24__19th IEEE Asian Test Symposium (ATS’10), IEEE, 2010, pp. 87–93, doi:10.1109/ats.2010.24.

Indlekofer, Thomas, et al. “Efficient Test Response Compaction for Robust BIST Using Parity Sequences.”10.1109/iccd.2010.5647648__28th IEEE International Conference on Computer Design (ICCD’10), IEEE, 2010, pp. 480–85, doi:10.1109/iccd.2010.5647648.

Hunger, Marc, and Sybille Hellebrand. “The Impact of Manufacturing Defects on the Fault Tolerance of TMR-Systems.”10.1109/dft.2010.19__25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’10), IEEE, 2010, pp. 101–08, doi:10.1109/dft.2010.19.

Froese, Viktor, et al. “Reusing NoC-Infrastructure for Test Data Compression.”10.1109/vts.2010.5469570__28th IEEE VLSI Test Symposium (VTS’10), IEEE, 2010, pp. 227–31, doi:10.1109/vts.2010.5469570.

Becker, Bernd, et al. “Massive Statistical Process Variations - A Grand Challenge for Testing Nanoelectronic Circuits.” 4th Workshop on Dependable and Secure Nanocomputing (WDSN’10), (Invited Paper), 2010.

Indlekofer, Thomas, et al. “Robuster Selbsttest Mit Extremer Kompaktierung.” 4. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf,” 2010, pp. 17–24.

Hunger, Marc, et al. “ATPG-Based Grading of Strong Fault-Secureness.”10.1109/iolts.2009.5196027__15th IEEE International On-Line Testing Symposium (IOLTS’09, IEEE, 2009, doi:10.1109/iolts.2009.5196027.

Hellebrand, Sybille, and Marc Hunger. “Are Robust Circuits Really Robust?”10.1109/dft.2009.28__24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’09), (Invited Talk), IEEE, 2009, p. 77, doi:10.1109/dft.2009.28.

Hunger, Marc, et al. “Robustheitsanalyse Stark Fehlersicherer Schaltungen Mit SAT-Basierter Testmustererzeugung.” 3. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf,” 2009.

Coym, Torsten, et al. Ein Verfeinertes Elektrisches Modell Für Teilchentreffer Und Dessen Auswirkung Auf Die Bewertung Der Schaltungsempfindlichkeit. 2008.

Amgalan, Uranmandakh, et al. Testen Mit Rücksetzpunkten - Ein Ansatz Zur Verbesserung Der Ausbeute Bei Robusten Schaltungen. 2008.

Oehler, Philipp, et al. “A Modular Memory BIST for Optimized Memory Repair.”10.1109/iolts.2008.30__14th IEEE International On-Line Testing Symposium (IOLTS’08), (Poster), IEEE, 2008, doi:10.1109/iolts.2008.30.

Amgalan, Uranmandakh, et al. “Signature Rollback - A Technique for Testing Robust Circuits.”10.1109/vts.2008.34__26th IEEE VLSI Test Symposium (VTS’08), IEEE, 2008, pp. 125–30, doi:10.1109/vts.2008.34.

Hunger, Marc, and Sybille Hellebrand. “Verification and Analysis of Self-Checking Properties through ATPG.”10.1109/iolts.2008.32__14th IEEE International On-Line Testing Symposium (IOLTS’08), IEEE, 2008, doi:10.1109/iolts.2008.32.

Hunger, Marc, and Sybille Hellebrand. “Analyse Selbstprüfender Schaltungen – Nachweis von Fehlersicherheit Und Selbsttestbarkeit Mit ATPG.” 2. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf,” 2008.

Oehler, Philipp, et al. “Modularer Selbsttest Und Optimierte Reparaturanalyse.” 2. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf,” 2008.

Hellebrand, Sybille. Reliable Nanoscale Systems - Challenges and Strategies for On- and Offline Testing. 2007.

Ali, Muhammad, et al. An End-to-End Reliability Protocol to Address Transient Faults in Network on Chips. 2007.

Oehler, Philipp, et al. An Integrated Built-in Test and Repair Approach for Memories with 2D Redundancy. 2007.

Hellebrand, Sybille. Qualitätssicherung Für Nanochips - Wie IT-Produkte Zuverlässig Werden. 2007.

Hellebrand, Sybille, et al. “A Refined Electrical Model for Particle Strikes and Its Impact on SEU Prediction.”10.1109/dft.2007.43__22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT’07), IEEE, 2007, pp. 50–58, doi:10.1109/dft.2007.43.

Oehler, Philipp, et al. “Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test and Repair.”10.1109/ddecs.2007.4295278__10th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS’07), IEEE, 2007, pp. 185–90, doi:10.1109/ddecs.2007.4295278.

Oehler, Philipp, et al. “An Integrated Built-In Test and Repair Approach for Memories with 2D Redundancy.”10.1109/ets.2007.10__12th IEEE European Test Symposium (ETS’07), IEEE, 2007, pp. 91–96, doi:10.1109/ets.2007.10.

Hellebrand, Sybille, et al. “Testing and Monitoring Nanoscale Systems - Challenges and Strategies for Advanced Quality Assurance.” 43rd International Conference on Microelectronics, Devices and Material with the Workshop on Electronic Testing (MIDEM’07), (Invited Paper), 2007.

Hellebrand, Sybille, et al. “Testing and Monitoring Nanoscale Systems - Challenges and Strategies for Advanced Quality Assurance.” Informacije MIDEM, Ljubljana (Invited Paper), vol. 37, no. 4 (124), 2007, pp. 212–19.

Ali, Muhammad, et al. “An Efficient Fault Tolerant Mechanism to Deal with Permanent and Transient Failures in a Network on Chip.” International Journal on High Performance Systems Architecture, vol. 1, no. 2, 2007, pp. 113–23.

Ali, Muhammad, et al. “A Fault Tolerant Mechanism for Handling Permanent and Transient Failures in a Network on Chip.” 4th International Conference on Information Technology: New Generations (ITNG’07), 2007, pp. 1027–32.

Becker, Bernd, et al. “Test Und Zuverlässigkeit Nanoelektronischer Systeme.” 1. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf,” 2007.