P. Oehler, S. Hellebrand, and H.-J. Wunderlich, An Integrated Built-in Test and Repair Approach for Memories with 2D Redundancy. 17th GI/ITG/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Erlangen, Germany, 2007.

S. Hellebrand, Qualitätssicherung für Nanochips - Wie IT-Produkte zuverlässig werden. ForschungsForum Paderborn, 10. Ausgabe, Paderborn, Germany, 2007.

S. Hellebrand, C. G. Zoellin, H.-J. Wunderlich, S. Ludwig, T. Coym, and B. Straube, “A Refined Electrical Model for Particle Strikes and its Impact on SEU Prediction,”10.1109/dft.2007.43__in 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT’07), 2007, pp. 50–58, doi:10.1109/dft.2007.43 .

P. Oehler, S. Hellebrand, and H.-J. Wunderlich, “Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test and Repair,”10.1109/ddecs.2007.4295278__in 10th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS’07), 2007, pp. 185–190, doi:10.1109/ddecs.2007.4295278 .

P. Oehler, S. Hellebrand, and H.-J. Wunderlich, “An Integrated Built-In Test and Repair Approach for Memories with 2D Redundancy,”10.1109/ets.2007.10__in 12th IEEE European Test Symposium (ETS’07), 2007, pp. 91–96, doi:10.1109/ets.2007.10 .

S. Hellebrand, C. G. Zoellin, H.-J. Wunderlich, S. Ludwig, T. Coym, and B. Straube, “Testing and Monitoring Nanoscale Systems - Challenges and Strategies for Advanced Quality Assurance,” 2007.

S. Hellebrand, C. G. Zoellin, H.-J. Wunderlich, S. Ludwig, T. Coym, and B. Straube, “Testing and Monitoring Nanoscale Systems - Challenges and Strategies for Advanced Quality Assurance,” Informacije MIDEM, Ljubljana (Invited Paper), vol. 37, no. 4 (124), pp. 212–219, 2007.

M. Ali, S. Hessler, M. Welzl, and S. Hellebrand, “An Efficient Fault Tolerant Mechanism to Deal with Permanent and Transient Failures in a Network on Chip,” International Journal on High Performance Systems Architecture, vol. 1, no. 2, pp. 113–123, 2007.

M. Ali, M. Welzl, S. Hessler, and S. Hellebrand, “A Fault Tolerant Mechanism for Handling Permanent and Transient Failures in a Network on Chip,” in 4th International Conference on Information Technology: New Generations (ITNG’07), 2007, pp. 1027–1032.

B. Becker, I. Polian, S. Hellebrand, B. Straube, and H.-J. Wunderlich, “Test und Zuverlässigkeit nanoelektronischer Systeme,” 2007.

B. Becker, I. Polian, S. Hellebrand, B. Straube, and H.-J. Wunderlich, “DFG-Projekt RealTest - Test und Zuverlässigkeit nanoelektronischer Systeme,” it - Information Technology, vol. 48, no. 5, pp. 305–311, 2006.

P. Oehler and S. Hellebrand, A Low Power Design for Embedded DRAMs with Online Consistency Checking. Kleinheubachertagung 2005, Miltenberg, Germany, 2005.

M. Ali, M. Welzl, and S. Hellebrand, Dynamic Routing: A Prerequisite for Reliable NoCs. 17th GI/ITG/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Innsbruck, Austria, 2005.

P. Oehler and S. Hellebrand, Power Consumption Versus Error Correcting Capabilities in Embedded DRAMs - A Case Study. 17th GI/ITG/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Innsbruck, Austria, 2005.

M. Ali, M. Welzl, M. Zwicknagl, and S. Hellebrand, “Considerations for Fault-Tolerant Networks on Chips,”10.1109/icm.2005.1590063__2005, doi:10.1109/icm.2005.1590063 .

P. Oehler and S. Hellebrand, “Low Power Embedded DRAMs with High Quality Error Correcting Capabilities,”10.1109/ets.2005.28__in 10th IEEE European Test Symposium (ETS’05), 2005, pp. 148–153, doi:10.1109/ets.2005.28 .

M. Ali, M. Welzl, and S. Hellebrand, “A Dynamic Routing Mechanism for Network on Chip,”10.1109/norchp.2005.1596991__in 23rd IEEE NORCHIP Conference, 2005, pp. 70–73, doi:10.1109/norchp.2005.1596991 .

M. Liu Jing et al., “Sensor Networks with More Features Using Less Hardware,” in GOR/NGB Conference Tilburg 2004, 2004.

R. Breu, T. Fahringer, D. Fensel, S. Hellebrand, A. Middeldorp, and O. Scherzer, Im Westen viel Neues - Informatik an der Universität Innsbruck. OCG Journal, pp. 28-29, 2004.

S. Hellebrand, A. Wuertenberger, and C. S. Tautermann, Data Compression for Multiple Scan Chains Using Dictionaries with Corrections. 9th IEEE European Test Symposium, Ajaccio, Corsica, France, 2004.

A. Wuertenberger, C. S. Tautermann, and S. Hellebrand, “Data Compression for Multiple Scan Chains Using Dictionaries with Corrections,”10.1109/test.2004.1387357__in IEEE International Test Conference (ITC’04), 2004, pp. 926–935, doi:10.1109/test.2004.1387357 .

R. Breu, S. Hellebrand, and M. Welzl, Experiences from Teaching Software Development in a Java Environment. Handouts ACS/IEEE Workshop on Practice and Experience with Java in Education, Tunis, Tunisia, 2003.

A. Wuertenberger, C. S. Tautermann, and S. Hellebrand, “A Hybrid Coding Strategy for Optimized Test Data Compression,”10.1109/test.2003.1270870__in IEEE International Test Conference (ITC’03), 2003, pp. 451–459, doi:10.1109/test.2003.1270870 .

S. Hellebrand and A. Wuertenberger, Alternating Run-Length Coding: A Technique for Improved Test Data Compression. IEEE International Workshop on Test Resource Partitioning, Baltimore, MD, USA, 2002.

S. Hellebrand, H.-J. Wunderlich, A. A. Ivaniuk, Y. V. Klimets, and V. N. Yarmolik, “Efficient Online and Offline Testing of Embedded DRAMs,”10.1109/tc.2002.1017700__IEEE Transactions on Computers, vol. 51, no. 7, pp. 801–809, 2002, doi:10.1109/tc.2002.1017700 .

S. Hellebrand, H.-G. Liang, and H.-J. Wunderlich, “Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST,” Journal of Electronic Testing - Theory and Applications (JETTA), vol. 18, no. 2, pp. 157–168, 2002.

H. Liang, S. Hellebrand, and H.-J. Wunderlich, “A Mixed-Mode BIST Scheme Based on Folding Compression,” Journal on Computer Science and Technology, vol. 17, no. 2, pp. 203–212, 2002.

H.-G. Liang, S. Hellebrand, and H.-J. Wunderlich, Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST. IEEE European Test Workshop, Stockholm, Sweden, 2001.

H.-G. Liang, S. Hellebrand, and H.-J. Wunderlich, “Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST,”10.1109/test.2001.966712__in IEEE International Test Conference (ITC’01), 2001, pp. 894–902, doi:10.1109/test.2001.966712 .

H.-G. Liang, S. Hellebrand, and H.-J. Wunderlich, “Deterministic BIST Scheme Based on Reseeding of Folding Counters,” Journal of Computer Research and Development, (Jisuanji Yanjiu yu Fazhan), vol. 38, no. 8, p. 931, 2001.

S. Hellebrand, H.-G. Liang, and H.-J. Wunderlich, “A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters,” Journal of Electronic Testing - Theory and Applications (JETTA), vol. 17, no. 3/4, pp. 341–349, 2001.

S. Hellebrand and H.-J. Wunderlich, Hardwarepraktikum im Diplomstudiengang Informatik. Handbuch Lehre, Berlin, Raabe Verlag, 2000.

S. Hellebrand, H.-G. Liang, and H.-J. Wunderlich, A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters. IEEE European Test Workshop, Cascais, Portugal, 2000.

S. Hellebrand, H.-G. Liang, and H.-J. Wunderlich, “A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters,”10.1109/test.2000.894274__in IEEE International Test Conference (ITC’00), 2000, pp. 778–784, doi:10.1109/test.2000.894274 .

S. Hellebrand, Selbsttestbare Steuerwerke - Strukturen und Syntheseverfahren. Verlag Dr. Kovac, Hamburg: Verlag Dr. Kovac, Hamburg, 1999.

S. Hellebrand, H.-J. Wunderlich, and V. N. Yarmolik, Exploiting Symmetries to Speed Up Transparent BIST. 11th GI/ITG/GMM/IEEE Workshop, 1999.

S. Hellebrand, H.-J. Wunderlich, A. A. Ivaniuk, Y. V. Klimets, and V. N. Yarmolik, “Error Detecting Refreshment for Embedded DRAMs,”10.1109/vtest.1999.766693__in 17th IEEE VLSI Test Symposium (VTS’99), 1999, pp. 384–390, doi:10.1109/vtest.1999.766693 .

V. N. Yarmolik, I. V. Bykov, S. Hellebrand, and H.-J. Wunderlich, “Transparent Word-Oriented Memory BIST Based on Symmetric March Algorithms,” 1999.

S. Hellebrand, H.-J. Wunderlich, and V. N. Yarmolik, “Symmetric Transparent BIST for RAMs,” in Design Automation and Test in Europe (DATE’99), 1999, pp. 702–707.

S. Hellebrand and H.-J. Wunderlich, Test und Synthese schneller eingebetteter Systeme. Universität Stuttgart, 1998.

V. N. Yarmolik, S. Hellebrand, and H.-J. Wunderlich, Efficient Consistency Checking for Embedded Memories. 5th IEEE International Test Synthesis Workshop, Santa Barbara, CA, USA, 1998.

V. N. Yarmolik, S. Hellebrand, and H.-J. Wunderlich, Efficient Consistency Checking for Embedded Memories. 10th GI/ITG/GMM/IEEE Workshop, 1998.

S. Hellebrand, H.-J. Wunderlich, and A. Hertwig, “Mixed-Mode BIST Using Embedded Processors,” in Mixed-Mode BIST Using Embedded Processors, In: M. Nicolaidis, Y. Zorian, D. K. Pradhan (Eds.): On-Line Testing for VLSI, Boston: Kluwer Academic Publishers 1998: Kluwer Academic Publishers, 1998.

S. Hellebrand, H.-J. Wunderlich, and A. Hertwig, “Mixed-Mode BIST Using Embedded Processors,” Journal of Electronic Testing Theory and Applications - JETTA, vol. 12, no. 1/2, pp. 127–138, 1998.

S. Hellebrand, A. Hertwig, and H.-J. Wunderlich, “Synthesis of Fast On-Line Testable Controllers for Data-Dominated Applications,” IEEE Design and Test, vol. 15, no. 4, pp. 36–41, 1998.

A. Hertwig, S. Hellebrand, and H.-J. Wunderlich, “Fast Self-Recovering Controllers,”10.1109/vtest.1998.670883__in 16th IEEE VLSI Test Symposium (VTS’98), 1998, pp. 296–302, doi:10.1109/vtest.1998.670883 .

S. Hellebrand, H.-J. Wunderlich, and V. N. Yarmolik, “Self-Adjusting Output Data Compression: An Efficient BIST Technique for RAMs,”10.1109/date.1998.655853__in Design Automation and Test in Europe (DATE’98), 1998, pp. 173–179, doi:10.1109/date.1998.655853 .

V. N. Yarmolik, Y. V. Klimets, S. Hellebrand, and H.-J. Wunderlich, “New Transparent RAM BIST Based on Self-Adjusting Output Data Compression,” in Design &; Diagnostics of Electronic Circuits &; Systems (DDECS’98), 1998, pp. 27–33.

K.-H. Tsai, S. Hellebrand, J. Rajski, and M. Marek-Sadowska, STARBIST: Scan Autocorrelated Random Pattern Generation. 4th IEEE International Test Synthesis Workshop, Santa Barbara, CA, USA, 1997.

A. Hertwig, S. Hellebrand, and H.-J. Wunderlich, Synthesis of Fast On-Line Testable Controllers for Data-Dominated Applications. 3rd IEEE International On-Line Testing Workshop, Crete, Greece, 1997.