A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters
S. Hellebrand, H.-G. Liang, H.-J. Wunderlich, Journal of Electronic Testing - Theory and Applications (JETTA) 17 (2001) 341–349.
LibreCat: /record/13068

Hardwarepraktikum im Diplomstudiengang Informatik
S. Hellebrand, H.-J. Wunderlich, Hardwarepraktikum Im Diplomstudiengang Informatik, Handbuch Lehre, Berlin, Raabe Verlag, 2000.
LibreCat: /record/13094

A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters
S. Hellebrand, H.-G. Liang, H.-J. Wunderlich, A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters, IEEE European Test Workshop, Cascais, Portugal, 2000.
LibreCat: /record/13095

A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters
S. Hellebrand, H.-G. Liang, H.-J. Wunderlich, in: IEEE International Test Conference (ITC’00), IEEE, Atlantic City, NJ, USA, 2000, pp. 778–784.
LibreCat: /record/13005
DOI: 10.1109/test.2000.894274

Selbsttestbare Steuerwerke - Strukturen und Syntheseverfahren
S. Hellebrand, Selbsttestbare Steuerwerke - Strukturen Und Syntheseverfahren, Verlag Dr. Kovac, Hamburg, Verlag Dr. Kovac, Hamburg, 1999.
LibreCat: /record/13065

Exploiting Symmetries to Speed Up Transparent BIST
S. Hellebrand, H.-J. Wunderlich, V. N. Yarmolik, Exploiting Symmetries to Speed Up Transparent BIST, 11th GI/ITG/GMM/IEEE Workshop, 1999.
LibreCat: /record/13093

Error Detecting Refreshment for Embedded DRAMs
S. Hellebrand, H.-J. Wunderlich, A. A. Ivaniuk, Y. V. Klimets, V. N. Yarmolik, in: 17th IEEE VLSI Test Symposium (VTS’99), IEEE, Dana Point, CA, USA, 1999, pp. 384–390.
LibreCat: /record/13006
DOI: 10.1109/vtest.1999.766693

Transparent Word-Oriented Memory BIST Based on Symmetric March Algorithms
V. N. Yarmolik, I. V. Bykov, S. Hellebrand, H.-J. Wunderlich, in: Third European Dependable Computing Conference (EDCC-3), Prague, Czech Republic, 1999.
LibreCat: /record/13066

Symmetric Transparent BIST for RAMs
S. Hellebrand, H.-J. Wunderlich, V. N. Yarmolik, in: Design Automation and Test in Europe (DATE’99), Munich, Germany, 1999, pp. 702–707.
LibreCat: /record/13067

Test und Synthese schneller eingebetteter Systeme
S. Hellebrand, H.-J. Wunderlich, Test Und Synthese Schneller Eingebetteter Systeme, Universität Stuttgart, 1998.
LibreCat: /record/13029

Efficient Consistency Checking for Embedded Memories
V. N. Yarmolik, S. Hellebrand, H.-J. Wunderlich, Efficient Consistency Checking for Embedded Memories, 5th IEEE International Test Synthesis Workshop, Santa Barbara, CA, USA, 1998.
LibreCat: /record/13091

Efficient Consistency Checking for Embedded Memories
V. N. Yarmolik, S. Hellebrand, H.-J. Wunderlich, Efficient Consistency Checking for Embedded Memories, 10th GI/ITG/GMM/IEEE Workshop, 1998.
LibreCat: /record/13092

Mixed-Mode BIST Using Embedded Processors
S. Hellebrand, H.-J. Wunderlich, A. Hertwig, in: Mixed-Mode BIST Using Embedded Processors, Kluwer Academic Publishers, In: M. Nicolaidis, Y. Zorian, D. K. Pradhan (Eds.): On-Line Testing for VLSI, Boston: Kluwer Academic Publishers 1998, 1998.
LibreCat: /record/13060

Mixed-Mode BIST Using Embedded Processors
S. Hellebrand, H.-J. Wunderlich, A. Hertwig, Journal of Electronic Testing Theory and Applications - JETTA 12 (1998) 127–138.
LibreCat: /record/13061

Synthesis of Fast On-Line Testable Controllers for Data-Dominated Applications
S. Hellebrand, A. Hertwig, H.-J. Wunderlich, IEEE Design and Test 15 (1998) 36–41.
LibreCat: /record/13064

Fast Self-Recovering Controllers
A. Hertwig, S. Hellebrand, H.-J. Wunderlich, in: 16th IEEE VLSI Test Symposium (VTS’98), IEEE, Monterey, CA, USA, 1998, pp. 296–302.
LibreCat: /record/13007
DOI: 10.1109/vtest.1998.670883

Self-Adjusting Output Data Compression: An Efficient BIST Technique for RAMs
S. Hellebrand, H.-J. Wunderlich, V. N. Yarmolik, in: Design Automation and Test in Europe (DATE’98), Paris, France, 1998, pp. 173–179.
LibreCat: /record/13008
DOI: 10.1109/date.1998.655853

New Transparent RAM BIST Based on Self-Adjusting Output Data Compression
V. N. Yarmolik, Y. V. Klimets, S. Hellebrand, H.-J. Wunderlich, in: Design &; Diagnostics of Electronic Circuits &; Systems (DDECS’98), Szczyrk, Poland, 1998, pp. 27–33.
LibreCat: /record/13063

STARBIST: Scan Autocorrelated Random Pattern Generation
K.-H. Tsai, S. Hellebrand, J. Rajski, M. Marek-Sadowska, STARBIST: Scan Autocorrelated Random Pattern Generation, 4th IEEE International Test Synthesis Workshop, Santa Barbara, CA, USA, 1997.
LibreCat: /record/13089

Synthesis of Fast On-Line Testable Controllers for Data-Dominated Applications
A. Hertwig, S. Hellebrand, H.-J. Wunderlich, Synthesis of Fast On-Line Testable Controllers for Data-Dominated Applications, 3rd IEEE International On-Line Testing Workshop, Crete, Greece, 1997.
LibreCat: /record/13090