Tsai, Kun-Han, et al. “STARBIST: Scan Autocorrelated Random Pattern Generation.”10.1109/dac.1997.597194__34th ACM/IEEE Design Automation Conference (DAC’97), IEEE, 1997, doi:10.1109/dac.1997.597194.
LibreCat: /record/13009
DOI: 10.1109/dac.1997.597194

Hellebrand, Sybille, and Hans-Joachim Wunderlich. Using Embedded Processors for BIST. 1996.
LibreCat: /record/13087

Hellebrand, Sybille, et al. Mixed-Mode BIST Using Embedded Processors. 1996.
LibreCat: /record/13088

Hellebrand, Sybille, et al. “Mixed-Mode BIST Using Embedded Processors.”10.1109/test.1996.556962__IEEE International Test Conference (ITC’96), IEEE, 1996, pp. 195–204, doi:10.1109/test.1996.556962.
LibreCat: /record/13010
DOI: 10.1109/test.1996.556962

Hellebrand, Sybille, and Hans-Joachim Wunderlich. Synthesis Procedures for Self-Testable Controllers. 1995.
LibreCat: /record/13026

Hellebrand, Sybille, et al. Evaluation of Self-Testable Controller Architectures Based on Realistic Fault Analysis. 1995.
LibreCat: /record/13027

Hellebrand, Sybille, et al. Partitioning of CMOS-Circuits for On-Chip IDDQ-Testing. 1995.
LibreCat: /record/13028

Hellebrand, Sybille, et al. Pattern Generation for a Deterministic BIST Scheme. 1995.
LibreCat: /record/13086

Hellebrand, Sybille, et al. “Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers.”10.1109/12.364534__IEEE Transactions on Computers, vol. 44, no. 2, IEEE, 1995, pp. 223–33, doi:10.1109/12.364534.
LibreCat: /record/13011
DOI: 10.1109/12.364534

Hellebrand, Sybille, et al. “Pattern Generation for a Deterministic BIST Scheme.”10.1109/iccad.1995.479997__ACM/IEEE International Conference on Computer Aided Design (ICCAD’95), IEEE, 1995, pp. 88–94, doi:10.1109/iccad.1995.479997.
LibreCat: /record/13012
DOI: 10.1109/iccad.1995.479997

Hellebrand, Sybille, et al. Synthesis for Off-Line Testability. 1994.
LibreCat: /record/13024

Hellebrand, Sybille, et al. Chip Level Test Planning for Controlling the Tradeoff between Hardware Overhead and Test Time. 1994.
LibreCat: /record/13025

Venkataraman, Srikanth, et al. Effiziente Testsatzkodierung Für Prüfpfad-Basierte Selbsttestarchitekturen. 1994.
LibreCat: /record/13083

Hellebrand, Sybille, and Hans-Joachim Wunderlich. Ein Verfahren Zur Testfreundlichen Steuerwerkssynthese. 1994.
LibreCat: /record/13084

Hellebrand, Sybille, et al. Synthesis for Testability - the ARCHIMEDES Approach. 1994.
LibreCat: /record/13085

Hellebrand, Sybille, and Hans-Joachim Wunderlich. “An Efficient Procedure for the Synthesis of Fast Self-Testable Controller Structures.”10.1109/iccad.1994.629752__ACM/IEEE International Conference on Computer-Aided Design (ICCAD’94), IEEE, 1994, pp. 110–16, doi:10.1109/iccad.1994.629752.
LibreCat: /record/13014
DOI: 10.1109/iccad.1994.629752

Hellebrand, Sybille, and Hans-Joachim Wunderlich. “Synthese Schneller Selbsttestbarer Steuerwerke.” Tagungsband Der GI/GME/ITG-Fachtagung \'26; Rechnergestützter Entwurf Und Architektur Mikroelektronischer Systeme, 1994, pp. 3–11.
LibreCat: /record/13059

Hellebrand, Sybille, and Hans-Joachim Wunderlich. “Synthesis of Self-Testable Controllers.”10.1109/edtc.1994.326815__European Design and Test Conference (EDAC/ETC/EUROASIC), 1994, pp. 580–85, doi:10.1109/edtc.1994.326815.
LibreCat: /record/13013
DOI: 10.1109/edtc.1994.326815

Hellebrand, Sybille, et al. Effiziente Erzeugung Deterministischer Muster Im Selbsttest. 1993.
LibreCat: /record/13081

Hellebrand, Sybille, and Hans-Joachim Wunderlich. Synthesis of Self-Testable Controllers. 1993.
LibreCat: /record/13082