DFG-Projekt RealTest - Test und Zuverlässigkeit nanoelektronischer Systeme
B. Becker, I. Polian, S. Hellebrand, B. Straube, H.-J. Wunderlich, It - Information Technology 48 (2006) 305–311.
LibreCat: /record/13045

A Low Power Design for Embedded DRAMs with Online Consistency Checking
P. Oehler, S. Hellebrand, A Low Power Design for Embedded DRAMs with Online Consistency Checking, Kleinheubachertagung 2005, Miltenberg, Germany, 2005.
LibreCat: /record/13046

Dynamic Routing: A Prerequisite for Reliable NoCs
M. Ali, M. Welzl, S. Hellebrand, Dynamic Routing: A Prerequisite for Reliable NoCs, 17th GI/ITG/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Innsbruck, Austria, 2005.
LibreCat: /record/13101

Power Consumption Versus Error Correcting Capabilities in Embedded DRAMs - A Case Study
P. Oehler, S. Hellebrand, Power Consumption Versus Error Correcting Capabilities in Embedded DRAMs - A Case Study, 17th GI/ITG/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Innsbruck, Austria, 2005.
LibreCat: /record/13102

Considerations for Fault-Tolerant Networks on Chips
M. Ali, M. Welzl, M. Zwicknagl, S. Hellebrand, in: IEEE International Conference on Microelectronics (ICM’05), IEEE, Islamabad, Pakistan, 2005.
LibreCat: /record/12999
DOI: 10.1109/icm.2005.1590063

Low Power Embedded DRAMs with High Quality Error Correcting Capabilities
P. Oehler, S. Hellebrand, in: 10th IEEE European Test Symposium (ETS’05), IEEE, Tallinn, Estonia, 2005, pp. 148–153.
LibreCat: /record/13000
DOI: 10.1109/ets.2005.28

A Dynamic Routing Mechanism for Network on Chip
M. Ali, M. Welzl, S. Hellebrand, in: 23rd IEEE NORCHIP Conference, IEEE, Oulu, Finland, 2005, pp. 70–73.
LibreCat: /record/12998
DOI: 10.1109/norchp.2005.1596991

Sensor Networks with More Features Using Less Hardware
M. Liu Jing, S. Ruehrup, C. Schindelhauer, K. Volbert, M. Dierkes, A. Bellgardt, R. Ibers, U. Hilleringmann, in: GOR/NGB Conference Tilburg 2004, Tilburg, Netherlands, 2004.
LibreCat: /record/13071

Im Westen viel Neues - Informatik an der Universität Innsbruck
R. Breu, T. Fahringer, D. Fensel, S. Hellebrand, A. Middeldorp, O. Scherzer, Im Westen Viel Neues - Informatik an Der Universität Innsbruck, OCG Journal, pp. 28-29, 2004.
LibreCat: /record/13099

Data Compression for Multiple Scan Chains Using Dictionaries with Corrections
S. Hellebrand, A. Wuertenberger, C. S. Tautermann, Data Compression for Multiple Scan Chains Using Dictionaries with Corrections, 9th IEEE European Test Symposium, Ajaccio, Corsica, France, 2004.
LibreCat: /record/13100

Data Compression for Multiple Scan Chains Using Dictionaries with Corrections
A. Wuertenberger, C. S. Tautermann, S. Hellebrand, in: IEEE International Test Conference (ITC’04), IEEE, Charlotte, NC, USA, 2004, pp. 926–935.
LibreCat: /record/13001
DOI: 10.1109/test.2004.1387357

Experiences from Teaching Software Development in a Java Environment
R. Breu, S. Hellebrand, M. Welzl, Experiences from Teaching Software Development in a Java Environment, Handouts ACS/IEEE Workshop on Practice and Experience with Java in Education, Tunis, Tunisia, 2003.
LibreCat: /record/13098

A Hybrid Coding Strategy for Optimized Test Data Compression
A. Wuertenberger, C. S. Tautermann, S. Hellebrand, in: IEEE International Test Conference (ITC’03), IEEE, Charlotte, NC, USA, 2003, pp. 451–459.
LibreCat: /record/13002
DOI: 10.1109/test.2003.1270870

Alternating Run-Length Coding: A Technique for Improved Test Data Compression
S. Hellebrand, A. Wuertenberger, Alternating Run-Length Coding: A Technique for Improved Test Data Compression, IEEE International Workshop on Test Resource Partitioning, Baltimore, MD, USA, 2002.
LibreCat: /record/13097

Efficient Online and Offline Testing of Embedded DRAMs
S. Hellebrand, H.-J. Wunderlich, A. A. Ivaniuk, Y. V. Klimets, V. N. Yarmolik, IEEE Transactions on Computers 51 (2002) 801–809.
LibreCat: /record/13003
DOI: 10.1109/tc.2002.1017700

Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST
S. Hellebrand, H.-G. Liang, H.-J. Wunderlich, Journal of Electronic Testing - Theory and Applications (JETTA) 18 (2002) 157–168.
LibreCat: /record/13069

A Mixed-Mode BIST Scheme Based on Folding Compression
H. Liang, S. Hellebrand, H.-J. Wunderlich, Journal on Computer Science and Technology 17 (2002) 203–212.
LibreCat: /record/13070

Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST
H.-G. Liang, S. Hellebrand, H.-J. Wunderlich, Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST, IEEE European Test Workshop, Stockholm, Sweden, 2001.
LibreCat: /record/13096

Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST
H.-G. Liang, S. Hellebrand, H.-J. Wunderlich, in: IEEE International Test Conference (ITC’01), IEEE, Baltimore, MD, USA, 2001, pp. 894–902.
LibreCat: /record/13004
DOI: 10.1109/test.2001.966712

Deterministic BIST Scheme Based on Reseeding of Folding Counters
H.-G. Liang, S. Hellebrand, H.-J. Wunderlich, Journal of Computer Research and Development, (Jisuanji Yanjiu Yu Fazhan) 38 (2001) 931.
LibreCat: /record/13047