M. Karp et al., “High-Performance Spectral Element Methods on Field-Programmable Gate Arraysf: Implementation, Evaluation, and Future Projection,”10.1109/ipdps49936.2021.00116__2021, doi:10.1109/ipdps49936.2021.00116 .
LibreCat: /record/46195
DOI: 10.1109/ipdps49936.2021.00116

S. Alhaddad et al., “HighPerMeshes – A Domain-Specific Language for Numerical Algorithms on Unstructured Grids,” in Euro-Par 2020: Parallel Processing Workshops, Cham, 2021.
LibreCat: /record/21587
DOI: 10.1007/978-3-030-71593-9_15

A. Ramaswami, T. Kenter, T. Kühne, and C. Plessl, “Evaluating the Design Space for Offloading 3D FFT Calculations to an FPGA for High-Performance Computing,” in Applied Reconfigurable Computing. Architectures, Tools, and Applications, Cham: Springer International Publishing, 2021.
LibreCat: /record/29936
DOI: 10.1007/978-3-030-79025-7_21

S. Alhaddad et al., “The HighPerMeshes framework for numerical algorithms on unstructured grids,”10.1002/cpe.6616__Concurrency and Computation: Practice and Experience, p. e6616, 2021, doi:10.1002/cpe.6616 .
LibreCat: /record/24788
DOI: 10.1002/cpe.6616

M. Karp et al., “High-Performance Spectral Element Methods on Field-Programmable Gate Arraysf: Implementation, Evaluation, and Future Projection,”10.1109/ipdps49936.2021.00116__2021, doi:10.1109/ipdps49936.2021.00116 .
LibreCat: /record/29937
DOI: 10.1109/ipdps49936.2021.00116

T. Kenter, A. Shambhu, S. Faghih-Naini, and V. Aizinger, “Algorithm-hardware co-design of a discontinuous Galerkin shallow-water model for a dataflow architecture on FPGA,”10.1145/3468267.3470617__2021, doi:10.1145/3468267.3470617 .
LibreCat: /record/46194
DOI: 10.1145/3468267.3470617

T. Kühne et al., “CK: An electronic structure and molecular dynamics software package - Quickstep: Efficient and accurate electronic structure calculations,”10.1063/5.0007045__The Journal of Chemical Physics, vol. 152, no. 19, Art. no. 194103, 2020, doi:10.1063/5.0007045 .
LibreCat: /record/16277
DOI: 10.1063/5.0007045
arXiv: 2003.03868

M. Lass, R. Schade, T. Kühne, and C. Plessl, “A Submatrix-Based Method for Approximate Matrix Function Evaluation in the Quantum Chemistry Code CK,”10.1109/SC41405.2020.00084__in Proc. International Conference for High Performance Computing, Networking, Storage and Analysis (SC), Atlanta, GA, US, 2020, pp. 1127–1140, doi:10.1109/SC41405.2020.00084 .
LibreCat: /record/16898
DOI: 10.1109/SC41405.2020.00084
arXiv: 2004.10811

M. Meyer, T. Kenter, and C. Plessl, “Evaluating FPGA Accelerator Performance with a Parameterized OpenCL Adaptation of Selected Benchmarks of the HPCChallenge Benchmark Suite,”10.1109/h2rc51942.2020.00007__2020, doi:10.1109/h2rc51942.2020.00007 .
LibreCat: /record/21632
DOI: 10.1109/h2rc51942.2020.00007

V. Rengaraj, M. Lass, C. Plessl, and T. Kühne, “Accurate Sampling with Noisy Forces from Approximate Computing,”10.3390/computation8020039__Computation, vol. 8, no. 2, Art. no. 39, 2020, doi:10.3390/computation8020039 .
LibreCat: /record/12878
DOI: 10.3390/computation8020039
arXiv: 1907.08497

H. Riebler, G. F. Vaz, T. Kenter, and C. Plessl, “Transparent Acceleration for Heterogeneous Platforms with Compilation to OpenCL,” ACM Trans. Archit. Code Optim. (TACO), vol. 16, no. 2, pp. 14:1–14:26, 2019.
LibreCat: /record/7689
DOI: 10.1145/3319423

P. Gorlani, T. Kenter, and C. Plessl, “OpenCL Implementation of Cannon’s Matrix Multiplication Algorithm on Intel Stratix 10 FPGAs,” in Proceedings of the International Conference on Field-Programmable Technology (FPT), 2019.
LibreCat: /record/15478
DOI: 10.1109/ICFPT47387.2019.00020

G. F. Vaz, Using Just-in-Time Code Generation to Transparently Accelerate Applications in Heterogeneous Systems. Universität Paderborn, 2019.
LibreCat: /record/14849

D. Richters, M. Lass, A. Walther, C. Plessl, and T. Kühne, “A General Algorithm to Calculate the Inverse Principal p-th Root of Symmetric Positive Definite Matrices,”10.4208/cicp.OA-2018-0053__Communications in Computational Physics, vol. 25, no. 2, pp. 564–585, 2019, doi:10.4208/cicp.OA-2018-0053 .
LibreCat: /record/21
DOI: 10.4208/cicp.OA-2018-0053
arXiv: 1703.02456

M. Platzner and C. Plessl, “FPGAs im Rechenzentrum,”10.1007/s00287-019-01187-w__Informatik Spektrum, 2019, doi:10.1007/s00287-019-01187-w .
LibreCat: /record/12871
DOI: 10.1007/s00287-019-01187-w

M. Lass, T. Kühne, and C. Plessl, “Using Approximate Computing for the Calculation of Inverse Matrix p-th Roots,” Embedded Systems Letters, vol. 10, no. 2, pp. 33–36, 2018.
LibreCat: /record/20
DOI: 10.1109/LES.2017.2760923
arXiv: 1703.02283

T. Filmwala, Study Effects of Approximation on Conjugate Gradient Algorithm and Accelerate it on FPGA Platform. Universität Paderborn, 2018.
LibreCat: /record/5414

O. Gadewar, Programmable Programs? - Designing FPGA Overlay Architectures with OpenCL. Universität Paderborn, 2018.
LibreCat: /record/5421

J. C. Mertens, A. Boschmann, M. Schmidt, and C. Plessl, “Sprint diagnostic with GPS and inertial sensor fusion,” Sports Engineering, vol. 21, no. 4, pp. 441–451, 2018.
LibreCat: /record/6516
DOI: 10.1007/s12283-018-0291-0

A. Ramaswami, Accelerating Molecular Dynamic Simulations by Offloading Fast Fourier Transformations to FPGA. Universität Paderborn, 2018.
LibreCat: /record/5417

T. Kenter et al., “OpenCL-based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured Meshes,”10.1109/FCCM.2018.00037__presented at the Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), 2018, doi:10.1109/FCCM.2018.00037 .
LibreCat: /record/1588
DOI: 10.1109/FCCM.2018.00037

M. Lass, S. Mohr, H. Wiebeler, T. Kühne, and C. Plessl, “A Massively Parallel Algorithm for the Approximate Calculation of Inverse p-th Roots of Large Sparse Matrices,”10.1145/3218176.3218231__presented at the Platform for Advanced Scientific Computing Conference (PASC), Basel, Switzerland, 2018, doi:10.1145/3218176.3218231 .
LibreCat: /record/1590
DOI: 10.1145/3218176.3218231
arXiv: 1710.10899

H. Riebler, G. F. Vaz, T. Kenter, and C. Plessl, “Automated Code Acceleration Targeting Heterogeneous OpenCL Devices,”10.1145/3178487.3178534__2018, doi:10.1145/3178487.3178534 .
LibreCat: /record/1204
DOI: 10.1145/3178487.3178534

H. Riebler, M. Lass, R. Mittendorf, T. Löcke, and C. Plessl, “Efficient Branch and Bound on FPGAs Using Work Stealing and Instance-Specific Designs,”10.1145/3053687__ACM Transactions on Reconfigurable Technology and Systems (TRETS), vol. 10, no. 3, p. 24:1-24:23, 2017, doi:10.1145/3053687 .
LibreCat: /record/18
DOI: 10.1145/3053687

T. Kenter, J. Förstner, and C. Plessl, “Flexible FPGA design for FDTD using OpenCL,”10.23919/FPL.2017.8056844__2017, doi:10.23919/FPL.2017.8056844 .
LibreCat: /record/1592
DOI: 10.23919/FPL.2017.8056844

J. Schumacher, C. Plessl, and W. Vandelli, “High-Throughput and Low-Latency Network Communication with NetIO,”10.1088/1742-6596/898/8/082003__Journal of Physics: Conference Series, vol. 898, Art. no. 082003, 2017, doi:10.1088/1742-6596/898/8/082003 .
LibreCat: /record/1589
DOI: 10.1088/1742-6596/898/8/082003

M. Lass, D. Leibenger, and C. Sorge, “Confidentiality and Authenticity for Distributed Version Control Systems - A Mercurial Extension,” in Proc. 41st Conference on Local Computer Networks (LCN), 2016.
LibreCat: /record/19
DOI: 10.1109/lcn.2016.11

C. Tölke, Sicherheit von hybriden FPGA-Systemen in der industriellen Automatisierungstechnik -- Anforderungen und Umsetzung. Universität Paderborn, 2016.
LibreCat: /record/5418

G. Wüllrich, Dynamic OpenCL Task Scheduling for Energy and Performance in a Heterogeneous Environment. Universität Paderborn, 2016.
LibreCat: /record/5420

T. Kenter, Reconfigurable Accelerators in the World of General-Purpose Computing. Universität Paderborn, 2016.
LibreCat: /record/161

A. Agne, M. Platzner, C. Plessl, M. Happe, and E. Lübbers, “ReconOS,” in FPGAs for Software Programmers, D. Koch, F. Hannig, and D. Ziener, Eds. Cham: Springer International Publishing, 2016, pp. 227–244.
LibreCat: /record/29
DOI: 10.1007/978-3-319-26408-0_13

H. Riebler, G. F. Vaz, C. Plessl, E. M. G. Trainiti, G. C. Durelli, and C. Bolchini, “Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems,” 2016.
LibreCat: /record/31

T. Kenter and C. Plessl, “Microdisk Cavity FDTD Simulation on FPGA using OpenCL,” 2016.
LibreCat: /record/24

M. Lass, T. Kühne, and C. Plessl, “Using Approximate Computing in Scientific Codes,” 2016.
LibreCat: /record/25

H. Riebler et al., “Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems,”10.1109/RTSI.2016.7740545__in Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI), 2016, pp. 1–5, doi:10.1109/RTSI.2016.7740545 .
LibreCat: /record/138
DOI: 10.1109/RTSI.2016.7740545

A. Agne, M. Happe, A. Lösch, C. Plessl, and M. Platzner, “Self-aware Compute Nodes,” in Self-aware Computing Systems, Cham: Springer International Publishing, 2016, pp. 145–165.
LibreCat: /record/156
DOI: 10.1007/978-3-319-39675-0_8

G. F. Vaz, H. Riebler, T. Kenter, and C. Plessl, “Potential and Methods for Embedding Dynamic Offloading Decisions into Application Code,”10.1016/j.compeleceng.2016.04.021__Computers and Electrical Engineering, vol. 55, pp. 91–111, 2016, doi:10.1016/j.compeleceng.2016.04.021 .
LibreCat: /record/165
DOI: 10.1016/j.compeleceng.2016.04.021

A. Lösch, T. Beisel, T. Kenter, C. Plessl, and M. Platzner, “Performance-centric scheduling with task migration for a heterogeneous compute node in the data center,” in Proceedings of the 2016 Design, Automation &; Test in Europe Conference &; Exhibition (DATE), 2016, pp. 912–917.
LibreCat: /record/168

T. Kenter, G. F. Vaz, H. Riebler, and C. Plessl, “Opportunities for deferring application partitioning and accelerator synthesis to runtime (extended abstract),” 2016.
LibreCat: /record/171

J. Torresen, C. Plessl, and X. Yao, “Self-Aware and Self-Expressive Systems – Guest Editor’s Introduction,” IEEE Computer, vol. 48, no. 7, pp. 18–20, 2015.
LibreCat: /record/1772
DOI: 10.1109/MC.2015.205

M. Lass, Localization and Analysis of Code Paths Suitable for Acceleration using Approximate Computing. Paderborn: Paderborn University, 2015.
LibreCat: /record/1794

T. Jenert and T. Brahm, “How Do They Find Their Place? A Longitudinal Study of Management Students’ Attitudes and Motivations During Their First Year at Business School,” presented at the American Educational Research Association (AERA) Annual Meeting 2015, Chicago, 2015.
LibreCat: /record/4465

L. Funke, An LLVM Based Toolchain for Transparent Acceleration of Digital Image Processing Applications using FPGA Overlay Architectures. Universität Paderborn, 2015.
LibreCat: /record/5413

T. Löcke, Instance-Specific Computing in Hard- and Software for Faster Solving of Complex Problems. Universität Paderborn, 2015.
LibreCat: /record/5416

F. Wallaschek, Accelerating Programmable Logic Controllers with the use of FPGAs. Universität Paderborn, 2015.
LibreCat: /record/5419

T. Beisel, Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing. Berlin: Logos Verlag Berlin GmbH, 2015.
LibreCat: /record/10624

T. Kenter, H. Schmitz, and C. Plessl, “Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study,”10.1155/2015/859425__International Journal of Reconfigurable Computing (IJRC), vol. 2015, Art. no. 859425, 2015, doi:10.1155/2015/859425 .
LibreCat: /record/296
DOI: 10.1155/2015/859425

M. Damschen and C. Plessl, “Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores,” 2015.
LibreCat: /record/303
arXiv: 1412.3906

J. Schumacher et al., “Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm,”10.1145/2675743.2771824__2015, doi:10.1145/2675743.2771824 .
LibreCat: /record/1773
DOI: 10.1145/2675743.2771824

C. Plessl, M. Platzner, and P. J. Schreier, “Aktuelles Schlagwort: Approximate Computing,”10.1007/s00287-015-0911-z__Informatik Spektrum, no. 5, pp. 396–399, 2015, doi:10.1007/s00287-015-0911-z .
LibreCat: /record/1768
DOI: 10.1007/s00287-015-0911-z

M. Damschen, H. Riebler, G. F. Vaz, and C. Plessl, “Transparent offloading of computational hotspots from binary code to Xeon Phi,”10.7873/DATE.2015.1124__in Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE), 2015, pp. 1078–1083, doi:10.7873/DATE.2015.1124 .
LibreCat: /record/238
DOI: 10.7873/DATE.2015.1124

J. Anderson et al., “FELIX: a High-Throughput Network Approach for Interfacing to Front End Electronics for ATLAS Upgrades,”10.1088/1742-6596/664/8/082050__Journal of Physics: Conference Series, vol. 664, Art. no. 082050, 2015, doi:10.1088/1742-6596/664/8/082050 .
LibreCat: /record/1775
DOI: 10.1088/1742-6596/664/8/082050

M. Platzner and C. Plessl, “Verschiebungen an der Grenze zwischen Hardware und Software,” in Logiken strukturbildender Prozesse: Automatismen, J. Künsemöller, N. O. Eke, L. Foit, and T. Kaerlein, Eds. Paderborn: Wilhelm Fink, 2014, pp. 123–144.
LibreCat: /record/335

T. Kenter, G. F. Vaz, and C. Plessl, “Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer,”10.1007/978-3-319-05960-0_13__in Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC), 2014, vol. 8405, pp. 144–155, doi:10.1007/978-3-319-05960-0_13 .
LibreCat: /record/388
DOI: 10.1007/978-3-319-05960-0_13

A. Agne, H. Hangmann, M. Happe, M. Platzner, and C. Plessl, “Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators,”10.1016/j.micpro.2013.12.001__Microprocessors and Microsystems, vol. 38, no. 8, Part B, pp. 911–919, 2014, doi:10.1016/j.micpro.2013.12.001 .
LibreCat: /record/363
DOI: 10.1016/j.micpro.2013.12.001

H. Riebler, T. Kenter, C. Plessl, and C. Sorge, “Reconstructing AES Key Schedules from Decayed Memory with FPGAs,”10.1109/FCCM.2014.67__in Proceedings of Field-Programmable Custom Computing Machines (FCCM), 2014, pp. 222–229, doi:10.1109/FCCM.2014.67 .
LibreCat: /record/377
DOI: 10.1109/FCCM.2014.67

A. Agne, M. Happe, A. Lösch, C. Plessl, and M. Platzner, “Self-awareness as a Model for Designing and Operating Heterogeneous Multicores,”10.1145/2617596__ACM Transactions on Reconfigurable Technology and Systems (TRETS), vol. 7, no. 2, Art. no. 13, 2014, doi:10.1145/2617596 .
LibreCat: /record/365
DOI: 10.1145/2617596

A. Agne et al., “ReconOS - An Operating System Approach for Reconfigurable Computing,”10.1109/MM.2013.110__IEEE Micro, vol. 34, no. 1, pp. 60–71, 2014, doi:10.1109/MM.2013.110 .
LibreCat: /record/328
DOI: 10.1109/MM.2013.110

G. C. Durelli et al., “Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach,”10.1109/ISPA.2014.27__in Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA), 2014, pp. 142–149, doi:10.1109/ISPA.2014.27 .
LibreCat: /record/1778
DOI: 10.1109/ISPA.2014.27

G. F. Vaz, H. Riebler, T. Kenter, and C. Plessl, “Deferring Accelerator Offloading Decisions to Application Runtime,”10.1109/ReConFig.2014.7032509__in Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 2014, pp. 1–8, doi:10.1109/ReConFig.2014.7032509 .
LibreCat: /record/439
DOI: 10.1109/ReConFig.2014.7032509

T. Kenter, H. Schmitz, and C. Plessl, “Kernel-Centric Acceleration of High Accuracy Stereo-Matching,”10.1109/ReConFig.2014.7032535__in Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 2014, pp. 1–8, doi:10.1109/ReConFig.2014.7032535 .
LibreCat: /record/406
DOI: 10.1109/ReConFig.2014.7032535

G. C. Durelli et al., “SAVE: Towards efficient resource management in heterogeneous system architectures,”10.1007/978-3-319-05960-0_38__2014, doi:10.1007/978-3-319-05960-0_38 .
LibreCat: /record/1780
DOI: 10.1007/978-3-319-05960-0_38

H. Giefers, C. Plessl, and J. Förstner, “Accelerating Finite Difference Time Domain Simulations with Reconfigurable Dataflow Computers,”10.1145/2641361.2641372__ACM SIGARCH Computer Architecture News, vol. 41, no. 5, pp. 65–70, 2014, doi:10.1145/2641361.2641372 .
LibreCat: /record/1779
DOI: 10.1145/2641361.2641372

H. Riebler, Identifikation und Wiederherstellung von kryptographischen Schlüsseln mit FPGAs. Universität Paderborn, 2013.
LibreCat: /record/521

H. Riebler, T. Kenter, C. Sorge, and C. Plessl, “FPGA-accelerated Key Search for Cold-Boot Attacks against AES,”10.1109/FPT.2013.6718394__in Proceedings of the International Conference on Field-Programmable Technology (FPT), 2013, pp. 386–389, doi:10.1109/FPT.2013.6718394 .
LibreCat: /record/528
DOI: 10.1109/FPT.2013.6718394

M. Happe, P. Kling, C. Plessl, M. Platzner, and F. Meyer auf der Heide, “On-The-Fly Computing: A Novel Paradigm for Individualized IT Services,”10.1109/ISORC.2013.6913232__2013, doi:10.1109/ISORC.2013.6913232 .
LibreCat: /record/505
DOI: 10.1109/ISORC.2013.6913232

T. Suess, A. Schoenrock, S. Meisner, and C. Plessl, “Parallel Macro Pipelining on the Intel SCC Many-Core Computer,”10.1109/IPDPSW.2013.136__in Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW), 2013, pp. 64–73, doi:10.1109/IPDPSW.2013.136 .
LibreCat: /record/1787
DOI: 10.1109/IPDPSW.2013.136

R. Grunzke et al., “A Data Driven Science Gateway for Computational Workflows,” in Proc. UNICORE Summit, 2012.
LibreCat: /record/2107

C. Plessl, M. Platzner, A. Agne, M. Happe, and E. Lübbers, Programming models for reconfigurable heterogeneous multi-cores. Awareness Magazine, 2012.
LibreCat: /record/587

B. Meyer, J. Schumacher, C. Plessl, and J. Förstner, “Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?,”10.1109/FPL.2012.6339370__in Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), 2012, pp. 189–196, doi:10.1109/FPL.2012.6339370 .
LibreCat: /record/2106
DOI: 10.1109/FPL.2012.6339370

T. Schumacher, C. Plessl, and M. Platzner, “IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators,”10.1016/j.micpro.2011.04.002__Microprocessors and Microsystems, vol. 36, no. 2, pp. 110–126, 2012, doi:10.1016/j.micpro.2011.04.002 .
LibreCat: /record/2108
DOI: 10.1016/j.micpro.2011.04.002

M. Happe, H. Hangmann, A. Agne, and C. Plessl, “Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators,”10.1109/ReConFig.2012.6416745__in Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), 2012, pp. 1–8, doi:10.1109/ReConFig.2012.6416745 .
LibreCat: /record/615
DOI: 10.1109/ReConFig.2012.6416745

T. Kenter, C. Plessl, and H. Schmitz, “Pragma based parallelization - Trading hardware efficiency for ease of use?,”10.1109/ReConFig.2012.6416773__in Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 2012, pp. 1–8, doi:10.1109/ReConFig.2012.6416773 .
LibreCat: /record/591
DOI: 10.1109/ReConFig.2012.6416773

M. Happe, A. Agne, C. Plessl, and M. Platzner, “Hardware/Software Platform for Self-aware Compute Nodes,” in Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS), 2012, pp. 8–9.
LibreCat: /record/609

P. Barrio, C. Carreras, R. Sierra, T. Kenter, and C. Plessl, “Turning control flow graphs into function calls: Code generation for heterogeneous architectures,”10.1109/HPCSim.2012.6266973__in Proceedings of the International Conference on High Performance Computing and Simulation (HPCS), 2012, pp. 559–565, doi:10.1109/HPCSim.2012.6266973 .
LibreCat: /record/567
DOI: 10.1109/HPCSim.2012.6266973

C. Rüthing, M. Happe, A. Agne, and C. Plessl, “Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs,”10.1109/FPL.2012.6339370__in Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), 2012, pp. 559–562, doi:10.1109/FPL.2012.6339370 .
LibreCat: /record/612
DOI: 10.1109/FPL.2012.6339370

T. Beisel, T. Wiersema, C. Plessl, and A. Brinkmann, “Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux,” 2012.
LibreCat: /record/2180

M. Grad and C. Plessl, “On the Feasibility and Limitations of Just-In-Time Instruction Set Extension for FPGA-based Reconfigurable Processors,”10.1155/2012/418315__Int. Journal of Reconfigurable Computing (IJRC), 2012, doi:10.1155/2012/418315 .
LibreCat: /record/2177
DOI: 10.1155/2012/418315

T. Kenter, C. Plessl, M. Platzner, and M. Kauschke, “Estimation and Partitioning for CPU-Accelerator Architectures,” in Intel European Research and Innovation Conference, 2011.
LibreCat: /record/2191

C. Plessl and M. Platzner, “Hardware Virtualization on Dynamically Reconfigurable Embedded Processors,” in Reconfigurable Embedded Control Systems: Applications for Flexibility and Agility, M. Khalgui and H.-M. Hanisch, Eds. Hershey, PA, USA: IGI Global, 2011.
LibreCat: /record/2202
DOI: 10.4018/978-1-60960-086-0

L. Sekanina, J. A. Walker, P. Kaufmann, C. Plessl, and M. Platzner, “Evolution of Electronic Circuits,” in Cartesian Genetic Programming, Springer Berlin Heidelberg, 2011, pp. 125–179.
LibreCat: /record/10737

B. Meyer, C. Plessl, and J. Förstner, “Transformation of scientific algorithms to parallel computing code: subdomain support in a MPI-multi-GPU backend,”10.1109/SAAHPC.2011.12__in Symp. on Application Accelerators in High Performance Computing (SAAHPC), 2011, pp. 60–63, doi:10.1109/SAAHPC.2011.12 .
LibreCat: /record/2194
DOI: 10.1109/SAAHPC.2011.12

T. Beisel, T. Wiersema, C. Plessl, and A. Brinkmann, “Cooperative multitasking for heterogeneous accelerators in the Linux Completely Fair Scheduler,”10.1109/ASAP.2011.6043273__in Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), 2011, pp. 223–226, doi:10.1109/ASAP.2011.6043273 .
LibreCat: /record/2193
DOI: 10.1109/ASAP.2011.6043273

M. Happe, A. Agne, and C. Plessl, “Measuring and Predicting Temperature Distributions on FPGAs at Run-Time,”10.1109/ReConFig.2011.59__in Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig), 2011, pp. 55–60, doi:10.1109/ReConFig.2011.59 .
LibreCat: /record/656
DOI: 10.1109/ReConFig.2011.59

T. Kenter, M. Platzner, C. Plessl, and M. Kauschke, “Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures,”10.1145/1950413.1950448__in Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA), 2011, pp. 177–180, doi:10.1145/1950413.1950448 .
LibreCat: /record/2200
DOI: 10.1145/1950413.1950448

T. Schumacher, T. Süß, C. Plessl, and M. Platzner, “FPGA Acceleration of Communication-bound Streaming Applications: Architecture Modeling and a 3D Image Compositing Case Study,”10.1155/2011/760954__Int. Journal of Recon- figurable Computing (IJRC), 2011, doi:10.1155/2011/760954 .
LibreCat: /record/2201
DOI: 10.1155/2011/760954

M. Grad and C. Plessl, “Just-in-time Instruction Set Extension – Feasibility and Limitations for an FPGA-based Reconfigurable ASIP Architecture,”10.1109/IPDPS.2011.153__in Proc. Reconfigurable Architectures Workshop (RAW), 2011, pp. 278–285, doi:10.1109/IPDPS.2011.153 .
LibreCat: /record/2198
DOI: 10.1109/IPDPS.2011.153

E. Lübbers, M. Platzner, C. Plessl, A. Keller, and B. Plattner, “Towards Adaptive Networking for Embedded Devices based on Reconfigurable Hardware,” in Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2010, pp. 225–231.
LibreCat: /record/2223

M. Grad and C. Plessl, “Pruning the Design Space for Just-In-Time Processor Customization,”10.1109/ReConFig.2010.19__in Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), 2010, pp. 67–72, doi:10.1109/ReConFig.2010.19 .
LibreCat: /record/2216
DOI: 10.1109/ReConFig.2010.19

M. Grad and C. Plessl, “An Open Source Circuit Library with Benchmarking Facilities,” in Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2010, pp. 144–150.
LibreCat: /record/2224

D. Andrews and C. Plessl, “Configurable Processor Architectures: History and Trends,” in Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2010, p. 165.
LibreCat: /record/2220

T. P. Plaks et al., Eds., Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press, 2010.
LibreCat: /record/2222

T. Beisel, M. Niekamp, and C. Plessl, “Using Shared Library Interposing for Transparent Acceleration in Systems with Heterogeneous Hardware Accelerators,”10.1109/ASAP.2010.5540798__in Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), 2010, pp. 65–72, doi:10.1109/ASAP.2010.5540798 .
LibreCat: /record/2226
DOI: 10.1109/ASAP.2010.5540798

A. Keller, B. Plattner, E. Lübbers, M. Platzner, and C. Plessl, “Reconfigurable Nodes for Future Networks,”10.1109/GLOCOMW.2010.5700341__in Proc. IEEE Globecom Workshop on Network of the Future (FutureNet), 2010, pp. 372–376, doi:10.1109/GLOCOMW.2010.5700341 .
LibreCat: /record/2206
DOI: 10.1109/GLOCOMW.2010.5700341

M. Woehrle, C. Plessl, and L. Thiele, “Rupeas: Ruby Powered Event Analysis DSL,”10.1109/INSS.2010.5572211__in Proc. Int. Conf. Networked Sensing Systems (INSS), 2010, pp. 245–248, doi:10.1109/INSS.2010.5572211 .
LibreCat: /record/2227
DOI: 10.1109/INSS.2010.5572211

T. Kenter, M. Platzner, C. Plessl, and M. Kauschke, “Performance Estimation for the Exploration of CPU-Accelerator Architectures,” in Proc. Workshop on Architectural Research Prototyping (WARP), International Symposium on Computer Architecture (ISCA), 2010.
LibreCat: /record/2228

M. Woehrle, C. Plessl, and L. Thiele, Rupeas: Ruby Powered Event Analysis DSL. Computer Engineering and Networks Lab, ETH Zurich, 2009.
LibreCat: /record/2353

T. Schumacher, C. Plessl, and M. Platzner, “IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing,”10.1109/FCCM.2009.25__in Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), 2009, pp. 275–278, doi:10.1109/FCCM.2009.25 .
LibreCat: /record/2350
DOI: 10.1109/FCCM.2009.25

P. Kaufmann, C. Plessl, and M. Platzner, “EvoCaches: Application-specific Adaptation of Cache Mapping,” in Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS), 2009, pp. 11–18.
LibreCat: /record/2262

J. Beutel et al., “PermaDAQ: A Scientific Instrument for Precision Sensing and Data Recovery in Environmental Extremes,” in Proc. Int. Conf. on Information Processing in Sensor Networks (IPSN), 2009, pp. 265–276.
LibreCat: /record/2352