B. Meyer, C. Plessl, and J. Förstner, “Transformation of scientific algorithms to parallel computing code: subdomain support in a MPI-multi-GPU backend,”10.1109/SAAHPC.2011.12__in Symp. on Application Accelerators in High Performance Computing (SAAHPC), 2011, pp. 60–63, doi:10.1109/SAAHPC.2011.12 .

T. Beisel, T. Wiersema, C. Plessl, and A. Brinkmann, “Cooperative multitasking for heterogeneous accelerators in the Linux Completely Fair Scheduler,”10.1109/ASAP.2011.6043273__in Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), 2011, pp. 223–226, doi:10.1109/ASAP.2011.6043273 .

M. Happe, A. Agne, and C. Plessl, “Measuring and Predicting Temperature Distributions on FPGAs at Run-Time,”10.1109/ReConFig.2011.59__in Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig), 2011, pp. 55–60, doi:10.1109/ReConFig.2011.59 .

T. Kenter, M. Platzner, C. Plessl, and M. Kauschke, “Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures,”10.1145/1950413.1950448__in Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA), 2011, pp. 177–180, doi:10.1145/1950413.1950448 .

T. Schumacher, T. Süß, C. Plessl, and M. Platzner, “FPGA Acceleration of Communication-bound Streaming Applications: Architecture Modeling and a 3D Image Compositing Case Study,”10.1155/2011/760954__Int. Journal of Recon- figurable Computing (IJRC), 2011, doi:10.1155/2011/760954 .

M. Grad and C. Plessl, “Just-in-time Instruction Set Extension – Feasibility and Limitations for an FPGA-based Reconfigurable ASIP Architecture,”10.1109/IPDPS.2011.153__in Proc. Reconfigurable Architectures Workshop (RAW), 2011, pp. 278–285, doi:10.1109/IPDPS.2011.153 .

E. Lübbers, M. Platzner, C. Plessl, A. Keller, and B. Plattner, “Towards Adaptive Networking for Embedded Devices based on Reconfigurable Hardware,” in Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2010, pp. 225–231.

M. Grad and C. Plessl, “Pruning the Design Space for Just-In-Time Processor Customization,”10.1109/ReConFig.2010.19__in Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), 2010, pp. 67–72, doi:10.1109/ReConFig.2010.19 .

M. Grad and C. Plessl, “An Open Source Circuit Library with Benchmarking Facilities,” in Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2010, pp. 144–150.

D. Andrews and C. Plessl, “Configurable Processor Architectures: History and Trends,” in Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2010, p. 165.

T. P. Plaks et al., Eds., Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press, 2010.

T. Beisel, M. Niekamp, and C. Plessl, “Using Shared Library Interposing for Transparent Acceleration in Systems with Heterogeneous Hardware Accelerators,”10.1109/ASAP.2010.5540798__in Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), 2010, pp. 65–72, doi:10.1109/ASAP.2010.5540798 .

A. Keller, B. Plattner, E. Lübbers, M. Platzner, and C. Plessl, “Reconfigurable Nodes for Future Networks,”10.1109/GLOCOMW.2010.5700341__in Proc. IEEE Globecom Workshop on Network of the Future (FutureNet), 2010, pp. 372–376, doi:10.1109/GLOCOMW.2010.5700341 .

M. Woehrle, C. Plessl, and L. Thiele, “Rupeas: Ruby Powered Event Analysis DSL,”10.1109/INSS.2010.5572211__in Proc. Int. Conf. Networked Sensing Systems (INSS), 2010, pp. 245–248, doi:10.1109/INSS.2010.5572211 .

T. Kenter, M. Platzner, C. Plessl, and M. Kauschke, “Performance Estimation for the Exploration of CPU-Accelerator Architectures,” in Proc. Workshop on Architectural Research Prototyping (WARP), International Symposium on Computer Architecture (ISCA), 2010.

M. Woehrle, C. Plessl, and L. Thiele, Rupeas: Ruby Powered Event Analysis DSL. Computer Engineering and Networks Lab, ETH Zurich, 2009.

T. Schumacher, C. Plessl, and M. Platzner, “IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing,”10.1109/FCCM.2009.25__in Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), 2009, pp. 275–278, doi:10.1109/FCCM.2009.25 .

P. Kaufmann, C. Plessl, and M. Platzner, “EvoCaches: Application-specific Adaptation of Cache Mapping,” in Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS), 2009, pp. 11–18.

J. Beutel et al., “PermaDAQ: A Scientific Instrument for Precision Sensing and Data Recovery in Environmental Extremes,” in Proc. Int. Conf. on Information Processing in Sensor Networks (IPSN), 2009, pp. 265–276.

T. Schumacher, T. Süß, C. Plessl, and M. Platzner, “Communication Performance Characterization for Reconfigurable Accelerator Design on the ,”10.1109/ReConFig.2009.32__in Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), 2009, pp. 119–124, doi:10.1109/ReConFig.2009.32 .

T. Schumacher, C. Plessl, and M. Platzner, “An Accelerator for k-th Nearest Neighbor Thinning Based on the IMORC Infrastructure,” in Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), 2009, pp. 338–344.

M. Grad and C. Plessl, “Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX,” in Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2009, pp. 319–322.

M. Woehrle, C. Plessl, R. Lim, J. Beutel, and L. Thiele, “EvAnT: Analysis and Checking of event traces for Wireless Sensor Networks,”10.1109/SUTC.2008.24__in IEEE Int. Conf. on Sensor Networks, Ubiquitous, and Trustworthy Computing (SUTC), 2008, pp. 201–208, doi:10.1109/SUTC.2008.24 .

T. Schumacher, R. Meiche, P. Kaufmann, E. Lübbers, C. Plessl, and M. Platzner, “A Hardware Accelerator for k-th Nearest Neighbor Thinning,” in Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2008, pp. 245–251.

T. Schumacher, C. Plessl, and M. Platzner, “IMORC: An infrastructure for performance monitoring and optimization of reconfigurable computers,” 2008.

J. Beutel, C. Plessl, and M. Woehrle, Increasing the Reliability of Wireless Sensor Networks with a Unit Testing Framework. Computer Engineering and Networks Laboratory, ETH Zurich, 2007.

M. Woehrle, C. Plessl, J. Beutel, and L. Thiele, “Increasing the Reliability of Wireless Sensor Networks with a Distributed Testing Framework,”10.1145/1278972.1278996__in Proc. Workshop on Embedded Networked Sensors (EmNets), 2007, pp. 93–97, doi:10.1145/1278972.1278996 .

J. Beutel et al., “Automated Wireless Sensor Network Testing,”10.1109/INSS.2007.4297445__in Proc. Int. Conf. Networked Sensing Systems (INSS), 2007, pp. 303–303, doi:10.1109/INSS.2007.4297445 .

C. Plessl, Hardware virtualization on a coarse-grained reconfigurable processor. Aachen, Germany: Shaker Verlag, 2006.

C. Plessl, M. Platzner, and L. Thiele, “Optimal Temporal Partitioning based on Slowdown and Retiming,” in Proc. Int. Conf. on Field Programmable Technology (ICFPT), 2006, pp. 345–348.

C. Plessl and M. Platzner, “Zippy – A coarse-grained reconfigurable array with support for hardware virtualization,” in Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), 2005, pp. 213–218.

R. Enzler, C. Plessl, and M. Platzner, “System-level performance evaluation of reconfigurable processors,” Microprocessors and Microsystems, vol. 29, no. 2–3, pp. 63–73, 2005.

C. Plessl and M. Platzner, “Virtualization of Hardware – Introduction and Survey,” in Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2004, pp. 63–69.

C. Plessl and M. Platzner, “TKDM – A Reconfigurable Co-processor in a PC’s Memory Slot,” in Proc. Int. Conf. on Field Programmable Technology (ICFPT), 2003, pp. 252–259.

C. Plessl et al., “The Case for Reconfigurable Hardware in Wearable Computing,” Personal and Ubiquitous Computing, vol. 7, no. 5, pp. 299–308, 2003.

C. Plessl and M. Platzner, “Instance-Specific Accelerators for Minimum Covering,” Journal of Supercomputing, vol. 26, no. 2, pp. 109–129, 2003.

R. Enzler, C. Plessl, and M. Platzner, “Virtualizing Hardware with Multi-Context Reconfigurable Arrays,” in Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), 2003, vol. 2778, pp. 151–160.

R. Enzler, C. Plessl, and M. Platzner, “Co-simulation of a Hybrid Multi-Context Architecture,” in Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2003, pp. 174–180.

C. Plessl, R. Enzler, H. Walder, J. Beutel, M. Platzner, and L. Thiele, “Reconfigurable Hardware in Wearable Computing Nodes,” in Proc. Int. Symp. on Wearable Computers (ISWC), 2002, pp. 215–222.

M. Dyer, C. Plessl, and M. Platzner, “Partially Reconfigurable Cores for Xilinx Virtex,” in Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), 2002, vol. 2438, pp. 292–301.

C. Plessl and M. Platzner, “Custom Computing Machines for the Set Covering Problem,” in Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), 2002, pp. 163–172.

C. Plessl and M. Platzner, “Instance-Specific Accelerators for Minimum Covering,” in Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2001, pp. 85–91.

C. Plessl and E. Wilde, “Server-Side-Techniken im Web – ein Überblick,” iX, pp. 88–93, 2001.

C. Plessl, Reconfigurable Accelerators for Minimum Covering. Computer Engineering and Networks Lab, ETH Zurich, Switzerland, 2001.

R. Enzler, M. Platzner, C. Plessl, L. Thiele, and G. Tröster, “Reconfigurable Processors for Handhelds and Wearables: Application Analysis,” in Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III, 2001, vol. 4525, pp. 135–146.

C. Plessl and S. Maurer, Hardware/Software Codesign in Speech Compression Applications. Computer Engineering and Networks Lab, ETH Zurich, Switzerland, 2000.