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Kenter, T., Schmitz, H., &; Plessl, C. (2014). Kernel-Centric Acceleration of High Accuracy Stereo-Matching. Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–8.https://doi.org/10.1109/ReConFig.2014.7032535 

C. Durelli, G., Copolla, M., Djafarian, K., Koranaros, G., Miele, A., Paolino, M., Pell, O., Plessl, C., D. Santambrogio, M., &; Bolchini, C. (2014). SAVE: Towards efficient resource management in heterogeneous system architectures. Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC).https://doi.org/10.1007/978-3-319-05960-0_38 

Giefers, H., Plessl, C., &; Förstner, J. (2014). Accelerating Finite Difference Time Domain Simulations with Reconfigurable Dataflow Computers. ACM SIGARCH Computer Architecture News, 41(5), 65–70.https://doi.org/10.1145/2641361.2641372 

Riebler, H. (2013). Identifikation und Wiederherstellung von kryptographischen Schlüsseln mit FPGAs. Universität Paderborn.

Riebler, H., Kenter, T., Sorge, C., &; Plessl, C. (2013). FPGA-accelerated Key Search for Cold-Boot Attacks against AES. Proceedings of the International Conference on Field-Programmable Technology (FPT), 386–389.https://doi.org/10.1109/FPT.2013.6718394 

Happe, M., Kling, P., Plessl, C., Platzner, M., &; Meyer auf der Heide, F. (2013). On-The-Fly Computing: A Novel Paradigm for Individualized IT Services. Proceedings of the 9th IEEE Workshop on Software Technology for Future Embedded and Ubiquitous Systems (SEUS).https://doi.org/10.1109/ISORC.2013.6913232 

Suess, T., Schoenrock, A., Meisner, S., &; Plessl, C. (2013). Parallel Macro Pipelining on the Intel SCC Many-Core Computer. Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW), 64–73.https://doi.org/10.1109/IPDPSW.2013.136 

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Plessl, C., Platzner, M., Agne, A., Happe, M., &; Lübbers, E. (2012). Programming models for reconfigurable heterogeneous multi-cores. Awareness Magazine.

Meyer, B., Schumacher, J., Plessl, C., &; Förstner, J. (2012). Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort? Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), 189–196.https://doi.org/10.1109/FPL.2012.6339370 

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Happe, M., Hangmann, H., Agne, A., &; Plessl, C. (2012). Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators. Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), 1–8.https://doi.org/10.1109/ReConFig.2012.6416745 

Kenter, T., Plessl, C., &; Schmitz, H. (2012). Pragma based parallelization - Trading hardware efficiency for ease of use? Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–8.https://doi.org/10.1109/ReConFig.2012.6416773 

Happe, M., Agne, A., Plessl, C., &; Platzner, M. (2012). Hardware/Software Platform for Self-aware Compute Nodes. Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS), 8–9.

Barrio, P., Carreras, C., Sierra, R., Kenter, T., &; Plessl, C. (2012). Turning control flow graphs into function calls: Code generation for heterogeneous architectures. Proceedings of the International Conference on High Performance Computing and Simulation (HPCS), 559–565.https://doi.org/10.1109/HPCSim.2012.6266973 

Rüthing, C., Happe, M., Agne, A., &; Plessl, C. (2012). Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs. Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), 559–562.https://doi.org/10.1109/FPL.2012.6339370 

Beisel, T., Wiersema, T., Plessl, C., &; Brinkmann, A. (2012). Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux. Proc. Workshop on Computer Architecture and Operating System Co-Design (CAOS).

Grad, M., &; Plessl, C. (2012). On the Feasibility and Limitations of Just-In-Time Instruction Set Extension for FPGA-based Reconfigurable Processors. Int. Journal of Reconfigurable Computing (IJRC).https://doi.org/10.1155/2012/418315 

Kenter, T., Plessl, C., Platzner, M., &; Kauschke, M. (2011). Estimation and Partitioning for CPU-Accelerator Architectures. In Intel European Research and Innovation Conference.

Plessl, C., &; Platzner, M. (2011). Hardware Virtualization on Dynamically Reconfigurable Embedded Processors. In M. Khalgui &; H.-M. Hanisch (Eds.), Reconfigurable Embedded Control Systems: Applications for Flexibility and Agility. Hershey, PA, USA: IGI Global.https://doi.org/10.4018/978-1-60960-086-0 

Sekanina, L., Walker, J. A., Kaufmann, P., Plessl, C., &; Platzner, M. (2011). Evolution of Electronic Circuits. In Cartesian Genetic Programming (pp. 125–179). Springer Berlin Heidelberg.

Meyer, B., Plessl, C., &; Förstner, J. (2011). Transformation of scientific algorithms to parallel computing code: subdomain support in a MPI-multi-GPU backend. Symp. on Application Accelerators in High Performance Computing (SAAHPC), 60–63.https://doi.org/10.1109/SAAHPC.2011.12 

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Grad, M., &; Plessl, C. (2011). Just-in-time Instruction Set Extension – Feasibility and Limitations for an FPGA-based Reconfigurable ASIP Architecture. Proc. Reconfigurable Architectures Workshop (RAW), 278–285.https://doi.org/10.1109/IPDPS.2011.153 

Lübbers, E., Platzner, M., Plessl, C., Keller, A., &; Plattner, B. (2010). Towards Adaptive Networking for Embedded Devices based on Reconfigurable Hardware. Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 225–231.

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Beisel, T., Niekamp, M., &; Plessl, C. (2010). Using Shared Library Interposing for Transparent Acceleration in Systems with Heterogeneous Hardware Accelerators. Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), 65–72.https://doi.org/10.1109/ASAP.2010.5540798 

Keller, A., Plattner, B., Lübbers, E., Platzner, M., &; Plessl, C. (2010). Reconfigurable Nodes for Future Networks. Proc. IEEE Globecom Workshop on Network of the Future (FutureNet), 372–376.https://doi.org/10.1109/GLOCOMW.2010.5700341 

Woehrle, M., Plessl, C., &; Thiele, L. (2010). Rupeas: Ruby Powered Event Analysis DSL. Proc. Int. Conf. Networked Sensing Systems (INSS), 245–248.https://doi.org/10.1109/INSS.2010.5572211 

Kenter, T., Platzner, M., Plessl, C., &; Kauschke, M. (2010). Performance Estimation for the Exploration of CPU-Accelerator Architectures. In O. Hammami &; S. Larrabee (Eds.), Proc. Workshop on Architectural Research Prototyping (WARP), International Symposium on Computer Architecture (ISCA).

Woehrle, M., Plessl, C., &; Thiele, L. (2009). Rupeas: Ruby Powered Event Analysis DSL. Computer Engineering and Networks Lab, ETH Zurich.

Schumacher, T., Plessl, C., &; Platzner, M. (2009). IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing. Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), 275–278.https://doi.org/10.1109/FCCM.2009.25 

Kaufmann, P., Plessl, C., &; Platzner, M. (2009). EvoCaches: Application-specific Adaptation of Cache Mapping. Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS), 11–18.

Beutel, J., Gruber, S., Hasler, A., Lim, R., Meier, A., Plessl, C., Talzi, I., Thiele, L., Tschudin, C., Woehrle, M., &; Yuecel, M. (2009). PermaDAQ: A Scientific Instrument for Precision Sensing and Data Recovery in Environmental Extremes. Proc. Int. Conf. on Information Processing in Sensor Networks (IPSN), 265–276.

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Schumacher, T., Plessl, C., &; Platzner, M. (2009). An Accelerator for k-th Nearest Neighbor Thinning Based on the IMORC Infrastructure. Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), 338–344.

Grad, M., &; Plessl, C. (2009). Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX. Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 319–322.

Woehrle, M., Plessl, C., Lim, R., Beutel, J., &; Thiele, L. (2008). EvAnT: Analysis and Checking of event traces for Wireless Sensor Networks. IEEE Int. Conf. on Sensor Networks, Ubiquitous, and Trustworthy Computing (SUTC), 201–208.https://doi.org/10.1109/SUTC.2008.24 

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Woehrle, M., Plessl, C., Beutel, J., &; Thiele, L. (2007). Increasing the Reliability of Wireless Sensor Networks with a Distributed Testing Framework. Proc. Workshop on Embedded Networked Sensors (EmNets), 93–97.https://doi.org/10.1145/1278972.1278996 

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Plessl, C. (2006). Hardware virtualization on a coarse-grained reconfigurable processor. Aachen, Germany: Shaker Verlag.https://doi.org/10.2370/9783832255619 

Plessl, C., Platzner, M., &; Thiele, L. (2006). Optimal Temporal Partitioning based on Slowdown and Retiming. In Proc. Int. Conf. on Field Programmable Technology (ICFPT) (pp. 345–348). IEEE Computer Society.https://doi.org/10.1109/FPT.2006.270344 

Plessl, C., &; Platzner, M. (2005). Zippy – A coarse-grained reconfigurable array with support for hardware virtualization. In Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP) (pp. 213–218). IEEE Computer Society.https://doi.org/10.1109/ASAP.2005.69 

Enzler, R., Plessl, C., &; Platzner, M. (2005). System-level performance evaluation of reconfigurable processors. Microprocessors and Microsystems, 29(2–3), 63–73.https://doi.org/10.1016/j.micpro.2004.06.004 

Plessl, C., &; Platzner, M. (2004). Virtualization of Hardware – Introduction and Survey. In Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) (pp. 63–69). CSREA Press.

Plessl, C., &; Platzner, M. (2003). TKDM – A Reconfigurable Co-processor in a PC’s Memory Slot. In Proc. Int. Conf. on Field Programmable Technology (ICFPT) (pp. 252–259). IEEE Computer Society.https://doi.org/10.1109/FPT.2003.1275755 

Plessl, C., Enzler, R., Walder, H., Beutel, J., Platzner, M., Thiele, L., &; Tröster, G. (2003). The Case for Reconfigurable Hardware in Wearable Computing. Personal and Ubiquitous Computing, 7(5), 299–308.https://doi.org/10.1007/s00779-003-0243-x 

Plessl, C., &; Platzner, M. (2003). Instance-Specific Accelerators for Minimum Covering. Journal of Supercomputing, 26(2), 109–129.https://doi.org/10.1023/a:1024443416592 

Enzler, R., Plessl, C., &; Platzner, M. (2003). Virtualizing Hardware with Multi-Context Reconfigurable Arrays. In Proc. Int. Conf. on Field Programmable Logic and Applications (FPL) (Vol. 2778, pp. 151–160). Springer.https://doi.org/10.1007/b12007 

Enzler, R., Plessl, C., &; Platzner, M. (2003). Co-simulation of a Hybrid Multi-Context Architecture. In Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) (pp. 174–180). CSREA Press.

Plessl, C., Enzler, R., Walder, H., Beutel, J., Platzner, M., &; Thiele, L. (2002). Reconfigurable Hardware in Wearable Computing Nodes. In Proc. Int. Symp. on Wearable Computers (ISWC) (pp. 215–222). IEEE Computer Society.https://doi.org/10.1109/ISWC.2002.1167250 

Dyer, M., Plessl, C., &; Platzner, M. (2002). Partially Reconfigurable Cores for Xilinx Virtex. In Proc. Int. Conf. on Field Programmable Logic and Applications (FPL) (Vol. 2438, pp. 292–301). Springer.https://doi.org/10.1007/3-540-46117-5 

Plessl, C., &; Platzner, M. (2002). Custom Computing Machines for the Set Covering Problem. In Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM) (pp. 163–172). IEEE Computer Society.https://doi.org/10.1109/FPGA.2002.1106671 

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Plessl, C., &; Wilde, E. (2001). Server-Side-Techniken im Web – ein Überblick. IX, 88–93.

Plessl, C. (2001). Reconfigurable Accelerators for Minimum Covering. Computer Engineering and Networks Lab, ETH Zurich, Switzerland.

Enzler, R., Platzner, M., Plessl, C., Thiele, L., &; Tröster, G. (2001). Reconfigurable Processors for Handhelds and Wearables: Application Analysis. In Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III (Vol. 4525, pp. 135–146).https://doi.org/10.1117/12.434376 

Plessl, C., &; Maurer, S. (2000). Hardware/Software Codesign in Speech Compression Applications. Computer Engineering and Networks Lab, ETH Zurich, Switzerland.