Sekanina, L., Walker, J. A., Kaufmann, P., Plessl, C., &; Platzner, M. (2011). Evolution of Electronic Circuits. In Cartesian Genetic Programming (pp. 125–179). Springer Berlin Heidelberg.
LibreCat: /record/10737

Meyer, B., Plessl, C., &; Förstner, J. (2011). Transformation of scientific algorithms to parallel computing code: subdomain support in a MPI-multi-GPU backend. Symp. on Application Accelerators in High Performance Computing (SAAHPC), 60–63.https://doi.org/10.1109/SAAHPC.2011.12 
LibreCat: /record/2194
DOI: 10.1109/SAAHPC.2011.12

Beisel, T., Wiersema, T., Plessl, C., &; Brinkmann, A. (2011). Cooperative multitasking for heterogeneous accelerators in the Linux Completely Fair Scheduler. Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), 223–226.https://doi.org/10.1109/ASAP.2011.6043273 
LibreCat: /record/2193
DOI: 10.1109/ASAP.2011.6043273

Happe, M., Agne, A., &; Plessl, C. (2011). Measuring and Predicting Temperature Distributions on FPGAs at Run-Time. Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig), 55–60.https://doi.org/10.1109/ReConFig.2011.59 
LibreCat: /record/656
DOI: 10.1109/ReConFig.2011.59

Kenter, T., Platzner, M., Plessl, C., &; Kauschke, M. (2011). Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures. Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA), 177–180.https://doi.org/10.1145/1950413.1950448 
LibreCat: /record/2200
DOI: 10.1145/1950413.1950448

Schumacher, T., Süß, T., Plessl, C., &; Platzner, M. (2011). FPGA Acceleration of Communication-bound Streaming Applications: Architecture Modeling and a 3D Image Compositing Case Study. Int. Journal of Recon- Figurable Computing (IJRC).https://doi.org/10.1155/2011/760954 
LibreCat: /record/2201
DOI: 10.1155/2011/760954

Grad, M., &; Plessl, C. (2011). Just-in-time Instruction Set Extension – Feasibility and Limitations for an FPGA-based Reconfigurable ASIP Architecture. Proc. Reconfigurable Architectures Workshop (RAW), 278–285.https://doi.org/10.1109/IPDPS.2011.153 
LibreCat: /record/2198
DOI: 10.1109/IPDPS.2011.153

Lübbers, E., Platzner, M., Plessl, C., Keller, A., &; Plattner, B. (2010). Towards Adaptive Networking for Embedded Devices based on Reconfigurable Hardware. Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 225–231.
LibreCat: /record/2223

Grad, M., &; Plessl, C. (2010). Pruning the Design Space for Just-In-Time Processor Customization. Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), 67–72.https://doi.org/10.1109/ReConFig.2010.19 
LibreCat: /record/2216
DOI: 10.1109/ReConFig.2010.19

Grad, M., &; Plessl, C. (2010). An Open Source Circuit Library with Benchmarking Facilities. Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 144–150.
LibreCat: /record/2224

Andrews, D., &; Plessl, C. (2010). Configurable Processor Architectures: History and Trends. Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 165.
LibreCat: /record/2220

Plaks, T. P., Andrews, D., DeMara, R., Lam, H., Lee, J., Plessl, C., &; Stitt, G. (Eds.). (2010). Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press.
LibreCat: /record/2222

Beisel, T., Niekamp, M., &; Plessl, C. (2010). Using Shared Library Interposing for Transparent Acceleration in Systems with Heterogeneous Hardware Accelerators. Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), 65–72.https://doi.org/10.1109/ASAP.2010.5540798 
LibreCat: /record/2226
DOI: 10.1109/ASAP.2010.5540798

Keller, A., Plattner, B., Lübbers, E., Platzner, M., &; Plessl, C. (2010). Reconfigurable Nodes for Future Networks. Proc. IEEE Globecom Workshop on Network of the Future (FutureNet), 372–376.https://doi.org/10.1109/GLOCOMW.2010.5700341 
LibreCat: /record/2206
DOI: 10.1109/GLOCOMW.2010.5700341

Woehrle, M., Plessl, C., &; Thiele, L. (2010). Rupeas: Ruby Powered Event Analysis DSL. Proc. Int. Conf. Networked Sensing Systems (INSS), 245–248.https://doi.org/10.1109/INSS.2010.5572211 
LibreCat: /record/2227
DOI: 10.1109/INSS.2010.5572211

Kenter, T., Platzner, M., Plessl, C., &; Kauschke, M. (2010). Performance Estimation for the Exploration of CPU-Accelerator Architectures. In O. Hammami &; S. Larrabee (Eds.), Proc. Workshop on Architectural Research Prototyping (WARP), International Symposium on Computer Architecture (ISCA).
LibreCat: /record/2228

Woehrle, M., Plessl, C., &; Thiele, L. (2009). Rupeas: Ruby Powered Event Analysis DSL. Computer Engineering and Networks Lab, ETH Zurich.
LibreCat: /record/2353

Schumacher, T., Plessl, C., &; Platzner, M. (2009). IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing. Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), 275–278.https://doi.org/10.1109/FCCM.2009.25 
LibreCat: /record/2350
DOI: 10.1109/FCCM.2009.25

Kaufmann, P., Plessl, C., &; Platzner, M. (2009). EvoCaches: Application-specific Adaptation of Cache Mapping. Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS), 11–18.
LibreCat: /record/2262

Beutel, J., Gruber, S., Hasler, A., Lim, R., Meier, A., Plessl, C., Talzi, I., Thiele, L., Tschudin, C., Woehrle, M., &; Yuecel, M. (2009). PermaDAQ: A Scientific Instrument for Precision Sensing and Data Recovery in Environmental Extremes. Proc. Int. Conf. on Information Processing in Sensor Networks (IPSN), 265–276.
LibreCat: /record/2352

Schumacher, T., Süß, T., Plessl, C., &; Platzner, M. (2009). Communication Performance Characterization for Reconfigurable Accelerator Design on the . Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), 119–124.https://doi.org/10.1109/ReConFig.2009.32 
LibreCat: /record/2238
DOI: 10.1109/ReConFig.2009.32

Schumacher, T., Plessl, C., &; Platzner, M. (2009). An Accelerator for k-th Nearest Neighbor Thinning Based on the IMORC Infrastructure. Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), 338–344.
LibreCat: /record/2261

Grad, M., &; Plessl, C. (2009). Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX. Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 319–322.
LibreCat: /record/2263

Woehrle, M., Plessl, C., Lim, R., Beutel, J., &; Thiele, L. (2008). EvAnT: Analysis and Checking of event traces for Wireless Sensor Networks. IEEE Int. Conf. on Sensor Networks, Ubiquitous, and Trustworthy Computing (SUTC), 201–208.https://doi.org/10.1109/SUTC.2008.24 
LibreCat: /record/2370
DOI: 10.1109/SUTC.2008.24

Schumacher, T., Meiche, R., Kaufmann, P., Lübbers, E., Plessl, C., &; Platzner, M. (2008). A Hardware Accelerator for k-th Nearest Neighbor Thinning. Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 245–251.
LibreCat: /record/2364

Schumacher, T., Plessl, C., &; Platzner, M. (2008). IMORC: An infrastructure for performance monitoring and optimization of reconfigurable computers. Many-Core and Reconfigurable Supercomputing Conference (MRSC).
LibreCat: /record/2372

Beutel, J., Plessl, C., &; Woehrle, M. (2007). Increasing the Reliability of Wireless Sensor Networks with a Unit Testing Framework. Computer Engineering and Networks Laboratory, ETH Zurich.
LibreCat: /record/2394

Woehrle, M., Plessl, C., Beutel, J., &; Thiele, L. (2007). Increasing the Reliability of Wireless Sensor Networks with a Distributed Testing Framework. Proc. Workshop on Embedded Networked Sensors (EmNets), 93–97.https://doi.org/10.1145/1278972.1278996 
LibreCat: /record/2392
DOI: 10.1145/1278972.1278996

Beutel, J., Dyer, M., Lim, R., Plessl, C., Woehrle, M., Yuecel, M., &; Thiele, L. (2007). Automated Wireless Sensor Network Testing. Proc. Int. Conf. Networked Sensing Systems (INSS), 303–303.https://doi.org/10.1109/INSS.2007.4297445 
LibreCat: /record/2393
DOI: 10.1109/INSS.2007.4297445

Plessl, C. (2006). Hardware virtualization on a coarse-grained reconfigurable processor. Aachen, Germany: Shaker Verlag.https://doi.org/10.2370/9783832255619 
LibreCat: /record/2404
DOI: 10.2370/9783832255619

Plessl, C., Platzner, M., &; Thiele, L. (2006). Optimal Temporal Partitioning based on Slowdown and Retiming. In Proc. Int. Conf. on Field Programmable Technology (ICFPT) (pp. 345–348). IEEE Computer Society.https://doi.org/10.1109/FPT.2006.270344 
LibreCat: /record/2401
DOI: 10.1109/FPT.2006.270344

Plessl, C., &; Platzner, M. (2005). Zippy – A coarse-grained reconfigurable array with support for hardware virtualization. In Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP) (pp. 213–218). IEEE Computer Society.https://doi.org/10.1109/ASAP.2005.69 
LibreCat: /record/2411
DOI: 10.1109/ASAP.2005.69

Enzler, R., Plessl, C., &; Platzner, M. (2005). System-level performance evaluation of reconfigurable processors. Microprocessors and Microsystems, 29(2–3), 63–73.https://doi.org/10.1016/j.micpro.2004.06.004 
LibreCat: /record/2412
DOI: 10.1016/j.micpro.2004.06.004

Plessl, C., &; Platzner, M. (2004). Virtualization of Hardware – Introduction and Survey. In Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) (pp. 63–69). CSREA Press.
LibreCat: /record/2415

Plessl, C., &; Platzner, M. (2003). TKDM – A Reconfigurable Co-processor in a PC’s Memory Slot. In Proc. Int. Conf. on Field Programmable Technology (ICFPT) (pp. 252–259). IEEE Computer Society.https://doi.org/10.1109/FPT.2003.1275755 
LibreCat: /record/2418
DOI: 10.1109/FPT.2003.1275755

Plessl, C., Enzler, R., Walder, H., Beutel, J., Platzner, M., Thiele, L., &; Tröster, G. (2003). The Case for Reconfigurable Hardware in Wearable Computing. Personal and Ubiquitous Computing, 7(5), 299–308.https://doi.org/10.1007/s00779-003-0243-x 
LibreCat: /record/2419
DOI: 10.1007/s00779-003-0243-x

Plessl, C., &; Platzner, M. (2003). Instance-Specific Accelerators for Minimum Covering. Journal of Supercomputing, 26(2), 109–129.https://doi.org/10.1023/a:1024443416592 
LibreCat: /record/2420
DOI: 10.1023/a:1024443416592

Enzler, R., Plessl, C., &; Platzner, M. (2003). Virtualizing Hardware with Multi-Context Reconfigurable Arrays. In Proc. Int. Conf. on Field Programmable Logic and Applications (FPL) (Vol. 2778, pp. 151–160). Springer.https://doi.org/10.1007/b12007 
LibreCat: /record/2421
DOI: 10.1007/b12007

Enzler, R., Plessl, C., &; Platzner, M. (2003). Co-simulation of a Hybrid Multi-Context Architecture. In Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) (pp. 174–180). CSREA Press.
LibreCat: /record/2422

Plessl, C., Enzler, R., Walder, H., Beutel, J., Platzner, M., &; Thiele, L. (2002). Reconfigurable Hardware in Wearable Computing Nodes. In Proc. Int. Symp. on Wearable Computers (ISWC) (pp. 215–222). IEEE Computer Society.https://doi.org/10.1109/ISWC.2002.1167250 
LibreCat: /record/2423
DOI: 10.1109/ISWC.2002.1167250

Dyer, M., Plessl, C., &; Platzner, M. (2002). Partially Reconfigurable Cores for Xilinx Virtex. In Proc. Int. Conf. on Field Programmable Logic and Applications (FPL) (Vol. 2438, pp. 292–301). Springer.https://doi.org/10.1007/3-540-46117-5 
LibreCat: /record/2424
DOI: 10.1007/3-540-46117-5

Plessl, C., &; Platzner, M. (2002). Custom Computing Machines for the Set Covering Problem. In Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM) (pp. 163–172). IEEE Computer Society.https://doi.org/10.1109/FPGA.2002.1106671 
LibreCat: /record/2425
DOI: 10.1109/FPGA.2002.1106671

Plessl, C., &; Platzner, M. (2001). Instance-Specific Accelerators for Minimum Covering. In Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) (pp. 85–91). CSREA Press.
LibreCat: /record/2428

Plessl, C., &; Wilde, E. (2001). Server-Side-Techniken im Web – ein Überblick. IX, 88–93.
LibreCat: /record/2429

Plessl, C. (2001). Reconfigurable Accelerators for Minimum Covering. Computer Engineering and Networks Lab, ETH Zurich, Switzerland.
LibreCat: /record/2430

Enzler, R., Platzner, M., Plessl, C., Thiele, L., &; Tröster, G. (2001). Reconfigurable Processors for Handhelds and Wearables: Application Analysis. In Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III (Vol. 4525, pp. 135–146).https://doi.org/10.1117/12.434376 
LibreCat: /record/2432
DOI: 10.1117/12.434376

Plessl, C., &; Maurer, S. (2000). Hardware/Software Codesign in Speech Compression Applications. Computer Engineering and Networks Lab, ETH Zurich, Switzerland.
LibreCat: /record/2433