Meyer, Björn, et al. “Transformation of Scientific Algorithms to Parallel Computing Code: Subdomain Support in a MPI-Multi-GPU Backend.”10.1109/SAAHPC.2011.12__Symp. on Application Accelerators in High Performance Computing (SAAHPC), IEEE Computer Society, 2011, pp. 60–63, doi:10.1109/SAAHPC.2011.12.
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DOI: 10.1109/SAAHPC.2011.12

Beisel, Tobias, et al. “Cooperative Multitasking for Heterogeneous Accelerators in the Linux Completely Fair Scheduler.”10.1109/ASAP.2011.6043273__Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), IEEE Computer Society, 2011, pp. 223–26, doi:10.1109/ASAP.2011.6043273.
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DOI: 10.1109/ASAP.2011.6043273

Happe, Markus, et al. “Measuring and Predicting Temperature Distributions on FPGAs at Run-Time.”10.1109/ReConFig.2011.59__Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig), IEEE, 2011, pp. 55–60, doi:10.1109/ReConFig.2011.59.
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DOI: 10.1109/ReConFig.2011.59

Kenter, Tobias, et al. “Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures.”10.1145/1950413.1950448__Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA), ACM, 2011, pp. 177–80, doi:10.1145/1950413.1950448.
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DOI: 10.1145/1950413.1950448

Schumacher, Tobias, et al. “FPGA Acceleration of Communication-Bound Streaming Applications: Architecture Modeling and a 3D Image Compositing Case Study.”10.1155/2011/760954__Int. Journal of Recon- Figurable Computing (IJRC), Hindawi Publishing Corp., 2011, doi:10.1155/2011/760954.
LibreCat: /record/2201
DOI: 10.1155/2011/760954

Grad, Mariusz, and Christian Plessl. “Just-in-Time Instruction Set Extension – Feasibility and Limitations for an FPGA-Based Reconfigurable ASIP Architecture.”10.1109/IPDPS.2011.153__Proc. Reconfigurable Architectures Workshop (RAW), IEEE Computer Society, 2011, pp. 278–85, doi:10.1109/IPDPS.2011.153.
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DOI: 10.1109/IPDPS.2011.153

Lübbers, Enno, et al. “Towards Adaptive Networking for Embedded Devices Based on Reconfigurable Hardware.” Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2010, pp. 225–31.
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Grad, Mariusz, and Christian Plessl. “Pruning the Design Space for Just-In-Time Processor Customization.”10.1109/ReConFig.2010.19__Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), IEEE Computer Society, 2010, pp. 67–72, doi:10.1109/ReConFig.2010.19.
LibreCat: /record/2216
DOI: 10.1109/ReConFig.2010.19

Grad, Mariusz, and Christian Plessl. “An Open Source Circuit Library with Benchmarking Facilities.” Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2010, pp. 144–50.
LibreCat: /record/2224

Andrews, David, and Christian Plessl. “Configurable Processor Architectures: History and Trends.” Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2010, p. 165.
LibreCat: /record/2220

Plaks, Toomas P., et al., editors. Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press, 2010.
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Beisel, Tobias, et al. “Using Shared Library Interposing for Transparent Acceleration in Systems with Heterogeneous Hardware Accelerators.”10.1109/ASAP.2010.5540798__Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), IEEE Computer Society, 2010, pp. 65–72, doi:10.1109/ASAP.2010.5540798.
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DOI: 10.1109/ASAP.2010.5540798

Keller, Ariane, et al. “Reconfigurable Nodes for Future Networks.”10.1109/GLOCOMW.2010.5700341__Proc. IEEE Globecom Workshop on Network of the Future (FutureNet), IEEE, 2010, pp. 372–76, doi:10.1109/GLOCOMW.2010.5700341.
LibreCat: /record/2206
DOI: 10.1109/GLOCOMW.2010.5700341

Woehrle, Matthias, et al. “Rupeas: Ruby Powered Event Analysis DSL.”10.1109/INSS.2010.5572211__Proc. Int. Conf. Networked Sensing Systems (INSS), IEEE, 2010, pp. 245–48, doi:10.1109/INSS.2010.5572211.
LibreCat: /record/2227
DOI: 10.1109/INSS.2010.5572211

Kenter, Tobias, et al. “Performance Estimation for the Exploration of CPU-Accelerator Architectures.” Proc. Workshop on Architectural Research Prototyping (WARP), International Symposium on Computer Architecture (ISCA), edited by Omar Hammami and Sandra Larrabee, 2010.
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Woehrle, Matthias, et al. Rupeas: Ruby Powered Event Analysis DSL. 2009.
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Schumacher, Tobias, et al. “IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing.”10.1109/FCCM.2009.25__Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), IEEE Computer Society, 2009, pp. 275–78, doi:10.1109/FCCM.2009.25.
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DOI: 10.1109/FCCM.2009.25

Kaufmann, Paul, et al. “EvoCaches: Application-Specific Adaptation of Cache Mapping.” Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS), IEEE Computer Society, 2009, pp. 11–18.
LibreCat: /record/2262

Beutel, Jan, et al. “PermaDAQ: A Scientific Instrument for Precision Sensing and Data Recovery in Environmental Extremes.” Proc. Int. Conf. on Information Processing in Sensor Networks (IPSN), IEEE Computer Society, 2009, pp. 265–76.
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Schumacher, Tobias, et al. “Communication Performance Characterization for Reconfigurable Accelerator Design on the .”10.1109/ReConFig.2009.32__Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), IEEE Computer Society, 2009, pp. 119–24, doi:10.1109/ReConFig.2009.32.
LibreCat: /record/2238
DOI: 10.1109/ReConFig.2009.32

Schumacher, Tobias, et al. “An Accelerator for K-Th Nearest Neighbor Thinning Based on the IMORC Infrastructure.” Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), IEEE, 2009, pp. 338–44.
LibreCat: /record/2261

Grad, Mariusz, and Christian Plessl. “Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX.” Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2009, pp. 319–22.
LibreCat: /record/2263

Woehrle, Matthias, et al. “EvAnT: Analysis and Checking of Event Traces for Wireless Sensor Networks.”10.1109/SUTC.2008.24__IEEE Int. Conf. on Sensor Networks, Ubiquitous, and Trustworthy Computing (SUTC), IEEE Computer Society, 2008, pp. 201–08, doi:10.1109/SUTC.2008.24.
LibreCat: /record/2370
DOI: 10.1109/SUTC.2008.24

Schumacher, Tobias, et al. “A Hardware Accelerator for K-Th Nearest Neighbor Thinning.” Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2008, pp. 245–51.
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Schumacher, Tobias, et al. “IMORC: An Infrastructure for Performance Monitoring and Optimization of Reconfigurable Computers.” Many-Core and Reconfigurable Supercomputing Conference (MRSC), 2008.
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Beutel, Jan, et al. Increasing the Reliability of Wireless Sensor Networks with a Unit Testing Framework. 2007.
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Woehrle, Matthias, et al. “Increasing the Reliability of Wireless Sensor Networks with a Distributed Testing Framework.”10.1145/1278972.1278996__Proc. Workshop on Embedded Networked Sensors (EmNets), ACM, 2007, pp. 93–97, doi:10.1145/1278972.1278996.
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DOI: 10.1145/1278972.1278996

Beutel, Jan, et al. “Automated Wireless Sensor Network Testing.”10.1109/INSS.2007.4297445__Proc. Int. Conf. Networked Sensing Systems (INSS), IEEE, 2007, pp. 303–303, doi:10.1109/INSS.2007.4297445.
LibreCat: /record/2393
DOI: 10.1109/INSS.2007.4297445

Plessl, Christian. Hardware Virtualization on a Coarse-Grained Reconfigurable Processor. Shaker Verlag, 2006, doi:10.2370/9783832255619.
LibreCat: /record/2404
DOI: 10.2370/9783832255619

Plessl, Christian, et al. “Optimal Temporal Partitioning Based on Slowdown and Retiming.”10.1109/FPT.2006.270344__Proc. Int. Conf. on Field Programmable Technology (ICFPT), IEEE Computer Society, 2006, pp. 345–48, doi:10.1109/FPT.2006.270344.
LibreCat: /record/2401
DOI: 10.1109/FPT.2006.270344

Plessl, Christian, and Marco Platzner. “Zippy – A Coarse-Grained Reconfigurable Array with Support for Hardware Virtualization.”10.1109/ASAP.2005.69__Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), IEEE Computer Society, 2005, pp. 213–18, doi:10.1109/ASAP.2005.69.
LibreCat: /record/2411
DOI: 10.1109/ASAP.2005.69

Enzler, Rolf, et al. “System-Level Performance Evaluation of Reconfigurable Processors.”10.1016/j.micpro.2004.06.004__Microprocessors and Microsystems, vol. 29, no. 2–3, Elsevier, 2005, pp. 63–73, doi:10.1016/j.micpro.2004.06.004.
LibreCat: /record/2412
DOI: 10.1016/j.micpro.2004.06.004

Plessl, Christian, and Marco Platzner. “Virtualization of Hardware – Introduction and Survey.” Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2004, pp. 63–69.
LibreCat: /record/2415

Plessl, Christian, and Marco Platzner. “TKDM – A Reconfigurable Co-Processor in a PC’s Memory Slot.”10.1109/FPT.2003.1275755__Proc. Int. Conf. on Field Programmable Technology (ICFPT), IEEE Computer Society, 2003, pp. 252–59, doi:10.1109/FPT.2003.1275755.
LibreCat: /record/2418
DOI: 10.1109/FPT.2003.1275755

Plessl, Christian, et al. “The Case for Reconfigurable Hardware in Wearable Computing.”10.1007/s00779-003-0243-x__Personal and Ubiquitous Computing, vol. 7, no. 5, Springer, 2003, pp. 299–308, doi:10.1007/s00779-003-0243-x.
LibreCat: /record/2419
DOI: 10.1007/s00779-003-0243-x

Plessl, Christian, and Marco Platzner. “Instance-Specific Accelerators for Minimum Covering.”10.1023/a:1024443416592__Journal of Supercomputing, vol. 26, no. 2, Kluwer Academic Publishers, 2003, pp. 109–29, doi:10.1023/a:1024443416592.
LibreCat: /record/2420
DOI: 10.1023/a:1024443416592

Enzler, Rolf, et al. “Virtualizing Hardware with Multi-Context Reconfigurable Arrays.”10.1007/b12007__Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), vol. 2778, Springer, 2003, pp. 151–60, doi:10.1007/b12007.
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DOI: 10.1007/b12007

Enzler, Rolf, et al. “Co-Simulation of a Hybrid Multi-Context Architecture.” Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2003, pp. 174–80.
LibreCat: /record/2422

Plessl, Christian, et al. “Reconfigurable Hardware in Wearable Computing Nodes.”10.1109/ISWC.2002.1167250__Proc. Int. Symp. on Wearable Computers (ISWC), IEEE Computer Society, 2002, pp. 215–22, doi:10.1109/ISWC.2002.1167250.
LibreCat: /record/2423
DOI: 10.1109/ISWC.2002.1167250

Dyer, Matthias, et al. “Partially Reconfigurable Cores for Xilinx Virtex.”10.1007/3-540-46117-5__Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), vol. 2438, Springer, 2002, pp. 292–301, doi:10.1007/3-540-46117-5.
LibreCat: /record/2424
DOI: 10.1007/3-540-46117-5

Plessl, Christian, and Marco Platzner. “Custom Computing Machines for the Set Covering Problem.”10.1109/FPGA.2002.1106671__Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), IEEE Computer Society, 2002, pp. 163–72, doi:10.1109/FPGA.2002.1106671.
LibreCat: /record/2425
DOI: 10.1109/FPGA.2002.1106671

Plessl, Christian, and Marco Platzner. “Instance-Specific Accelerators for Minimum Covering.” Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2001, pp. 85–91.
LibreCat: /record/2428

Plessl, Christian, and Erik Wilde. “Server-Side-Techniken Im Web – Ein Überblick.” IX, Heise Verlag, 2001, pp. 88–93.
LibreCat: /record/2429

Plessl, Christian. Reconfigurable Accelerators for Minimum Covering. Computer Engineering and Networks Lab, ETH Zurich, Switzerland, 2001.
LibreCat: /record/2430

Enzler, Rolf, et al. “Reconfigurable Processors for Handhelds and Wearables: Application Analysis.”10.1117/12.434376__Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III, vol. 4525, 2001, pp. 135–46, doi:10.1117/12.434376.
LibreCat: /record/2432
DOI: 10.1117/12.434376

Plessl, Christian, and Simon Maurer. Hardware/Software Codesign in Speech Compression Applications. Computer Engineering and Networks Lab, ETH Zurich, Switzerland, 2000.
LibreCat: /record/2433