Schumacher T, Plessl C, Platzner M. IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators. Microprocessors and Microsystems. 2012;36(2):110-126. doi:10.1016/j.micpro.2011.04.002
LibreCat: /record/2108
DOI: 10.1016/j.micpro.2011.04.002

Happe M, Hangmann H, Agne A, Plessl C. Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators. In: Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig). IEEE; 2012:1-8. doi:10.1109/ReConFig.2012.6416745
LibreCat: /record/615
DOI: 10.1109/ReConFig.2012.6416745

Kenter T, Plessl C, Schmitz H. Pragma based parallelization - Trading hardware efficiency for ease of use? In: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE; 2012:1-8. doi:10.1109/ReConFig.2012.6416773
LibreCat: /record/591
DOI: 10.1109/ReConFig.2012.6416773

Happe M, Agne A, Plessl C, Platzner M. Hardware/Software Platform for Self-aware Compute Nodes. In: Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS). ; 2012:8-9.
LibreCat: /record/609

Barrio P, Carreras C, Sierra R, Kenter T, Plessl C. Turning control flow graphs into function calls: Code generation for heterogeneous architectures. In: Proceedings of the International Conference on High Performance Computing and Simulation (HPCS). IEEE; 2012:559-565. doi:10.1109/HPCSim.2012.6266973
LibreCat: /record/567
DOI: 10.1109/HPCSim.2012.6266973

Rüthing C, Happe M, Agne A, Plessl C. Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs. In: Proceedings of the International Conference on Field Programmable Logic and Applications (FPL). IEEE; 2012:559-562. doi:10.1109/FPL.2012.6339370
LibreCat: /record/612
DOI: 10.1109/FPL.2012.6339370

Beisel T, Wiersema T, Plessl C, Brinkmann A. Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux. In: Proc. Workshop on Computer Architecture and Operating System Co-Design (CAOS). ; 2012.
LibreCat: /record/2180

Grad M, Plessl C. On the Feasibility and Limitations of Just-In-Time Instruction Set Extension for FPGA-based Reconfigurable Processors. Int Journal of Reconfigurable Computing (IJRC). Published online 2012. doi:10.1155/2012/418315
LibreCat: /record/2177
DOI: 10.1155/2012/418315

Kenter T, Plessl C, Platzner M, Kauschke M. Estimation and Partitioning for CPU-Accelerator Architectures. In: Intel European Research and Innovation Conference. ; 2011.
LibreCat: /record/2191

Plessl C, Platzner M. Hardware Virtualization on Dynamically Reconfigurable Embedded Processors. In: Khalgui M, Hanisch H-M, eds. Reconfigurable Embedded Control Systems: Applications for Flexibility and Agility. Hershey, PA, USA: IGI Global; 2011. doi:10.4018/978-1-60960-086-0
LibreCat: /record/2202
DOI: 10.4018/978-1-60960-086-0

Sekanina L, Walker JA, Kaufmann P, Plessl C, Platzner M. Evolution of Electronic Circuits. In: Cartesian Genetic Programming. Natural Computing Series. Springer Berlin Heidelberg; 2011:125-179.
LibreCat: /record/10737

Meyer B, Plessl C, Förstner J. Transformation of scientific algorithms to parallel computing code: subdomain support in a MPI-multi-GPU backend. In: Symp. on Application Accelerators in High Performance Computing (SAAHPC). IEEE Computer Society; 2011:60-63. doi:10.1109/SAAHPC.2011.12
LibreCat: /record/2194
DOI: 10.1109/SAAHPC.2011.12

Beisel T, Wiersema T, Plessl C, Brinkmann A. Cooperative multitasking for heterogeneous accelerators in the Linux Completely Fair Scheduler. In: Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP). IEEE Computer Society; 2011:223-226. doi:10.1109/ASAP.2011.6043273
LibreCat: /record/2193
DOI: 10.1109/ASAP.2011.6043273

Happe M, Agne A, Plessl C. Measuring and Predicting Temperature Distributions on FPGAs at Run-Time. In: Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig). IEEE; 2011:55-60. doi:10.1109/ReConFig.2011.59
LibreCat: /record/656
DOI: 10.1109/ReConFig.2011.59

Kenter T, Platzner M, Plessl C, Kauschke M. Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures. In: Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA). ACM; 2011:177-180. doi:10.1145/1950413.1950448
LibreCat: /record/2200
DOI: 10.1145/1950413.1950448

Schumacher T, Süß T, Plessl C, Platzner M. FPGA Acceleration of Communication-bound Streaming Applications: Architecture Modeling and a 3D Image Compositing Case Study. Int Journal of Recon- figurable Computing (IJRC). Published online 2011. doi:10.1155/2011/760954
LibreCat: /record/2201
DOI: 10.1155/2011/760954

Grad M, Plessl C. Just-in-time Instruction Set Extension – Feasibility and Limitations for an FPGA-based Reconfigurable ASIP Architecture. In: Proc. Reconfigurable Architectures Workshop (RAW). IEEE Computer Society; 2011:278-285. doi:10.1109/IPDPS.2011.153
LibreCat: /record/2198
DOI: 10.1109/IPDPS.2011.153

Lübbers E, Platzner M, Plessl C, Keller A, Plattner B. Towards Adaptive Networking for Embedded Devices based on Reconfigurable Hardware. In: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press; 2010:225-231.
LibreCat: /record/2223

Grad M, Plessl C. Pruning the Design Space for Just-In-Time Processor Customization. In: Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig). IEEE Computer Society; 2010:67-72. doi:10.1109/ReConFig.2010.19
LibreCat: /record/2216
DOI: 10.1109/ReConFig.2010.19

Grad M, Plessl C. An Open Source Circuit Library with Benchmarking Facilities. In: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press; 2010:144-150.
LibreCat: /record/2224

Andrews D, Plessl C. Configurable Processor Architectures: History and Trends. In: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press; 2010:165.
LibreCat: /record/2220

Plaks TP, Andrews D, DeMara R, et al., eds. Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press; 2010.
LibreCat: /record/2222

Beisel T, Niekamp M, Plessl C. Using Shared Library Interposing for Transparent Acceleration in Systems with Heterogeneous Hardware Accelerators. In: Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP). IEEE Computer Society; 2010:65-72. doi:10.1109/ASAP.2010.5540798
LibreCat: /record/2226
DOI: 10.1109/ASAP.2010.5540798

Keller A, Plattner B, Lübbers E, Platzner M, Plessl C. Reconfigurable Nodes for Future Networks. In: Proc. IEEE Globecom Workshop on Network of the Future (FutureNet). IEEE; 2010:372-376. doi:10.1109/GLOCOMW.2010.5700341
LibreCat: /record/2206
DOI: 10.1109/GLOCOMW.2010.5700341

Woehrle M, Plessl C, Thiele L. Rupeas: Ruby Powered Event Analysis DSL. In: Proc. Int. Conf. Networked Sensing Systems (INSS). IEEE; 2010:245-248. doi:10.1109/INSS.2010.5572211
LibreCat: /record/2227
DOI: 10.1109/INSS.2010.5572211

Kenter T, Platzner M, Plessl C, Kauschke M. Performance Estimation for the Exploration of CPU-Accelerator Architectures. In: Hammami O, Larrabee S, eds. Proc. Workshop on Architectural Research Prototyping (WARP), International Symposium on Computer Architecture (ISCA). ; 2010.
LibreCat: /record/2228

Woehrle M, Plessl C, Thiele L. Rupeas: Ruby Powered Event Analysis DSL. Computer Engineering and Networks Lab, ETH Zurich; 2009.
LibreCat: /record/2353

Schumacher T, Plessl C, Platzner M. IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing. In: Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM). IEEE Computer Society; 2009:275-278. doi:10.1109/FCCM.2009.25
LibreCat: /record/2350
DOI: 10.1109/FCCM.2009.25

Kaufmann P, Plessl C, Platzner M. EvoCaches: Application-specific Adaptation of Cache Mapping. In: Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS). IEEE Computer Society; 2009:11-18.
LibreCat: /record/2262

Beutel J, Gruber S, Hasler A, et al. PermaDAQ: A Scientific Instrument for Precision Sensing and Data Recovery in Environmental Extremes. In: Proc. Int. Conf. on Information Processing in Sensor Networks (IPSN). IEEE Computer Society; 2009:265-276.
LibreCat: /record/2352

Schumacher T, Süß T, Plessl C, Platzner M. Communication Performance Characterization for Reconfigurable Accelerator Design on the . In: Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig). IEEE Computer Society; 2009:119-124. doi:10.1109/ReConFig.2009.32
LibreCat: /record/2238
DOI: 10.1109/ReConFig.2009.32

Schumacher T, Plessl C, Platzner M. An Accelerator for k-th Nearest Neighbor Thinning Based on the IMORC Infrastructure. In: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL). IEEE; 2009:338-344.
LibreCat: /record/2261

Grad M, Plessl C. Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX. In: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press; 2009:319-322.
LibreCat: /record/2263

Woehrle M, Plessl C, Lim R, Beutel J, Thiele L. EvAnT: Analysis and Checking of event traces for Wireless Sensor Networks. In: IEEE Int. Conf. on Sensor Networks, Ubiquitous, and Trustworthy Computing (SUTC). IEEE Computer Society; 2008:201-208. doi:10.1109/SUTC.2008.24
LibreCat: /record/2370
DOI: 10.1109/SUTC.2008.24

Schumacher T, Meiche R, Kaufmann P, Lübbers E, Plessl C, Platzner M. A Hardware Accelerator for k-th Nearest Neighbor Thinning. In: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press; 2008:245-251.
LibreCat: /record/2364

Schumacher T, Plessl C, Platzner M. IMORC: An infrastructure for performance monitoring and optimization of reconfigurable computers. In: Many-Core and Reconfigurable Supercomputing Conference (MRSC). ; 2008.
LibreCat: /record/2372

Beutel J, Plessl C, Woehrle M. Increasing the Reliability of Wireless Sensor Networks with a Unit Testing Framework. Computer Engineering and Networks Laboratory, ETH Zurich; 2007.
LibreCat: /record/2394

Woehrle M, Plessl C, Beutel J, Thiele L. Increasing the Reliability of Wireless Sensor Networks with a Distributed Testing Framework. In: Proc. Workshop on Embedded Networked Sensors (EmNets). ACM; 2007:93-97. doi:10.1145/1278972.1278996
LibreCat: /record/2392
DOI: 10.1145/1278972.1278996

Beutel J, Dyer M, Lim R, et al. Automated Wireless Sensor Network Testing. In: Proc. Int. Conf. Networked Sensing Systems (INSS). IEEE; 2007:303-303. doi:10.1109/INSS.2007.4297445
LibreCat: /record/2393
DOI: 10.1109/INSS.2007.4297445

Plessl C. Hardware Virtualization on a Coarse-Grained Reconfigurable Processor. Aachen, Germany: Shaker Verlag; 2006. doi:10.2370/9783832255619
LibreCat: /record/2404
DOI: 10.2370/9783832255619

Plessl C, Platzner M, Thiele L. Optimal Temporal Partitioning based on Slowdown and Retiming. In: Proc. Int. Conf. on Field Programmable Technology (ICFPT). IEEE Computer Society; 2006:345-348. doi:10.1109/FPT.2006.270344
LibreCat: /record/2401
DOI: 10.1109/FPT.2006.270344

Plessl C, Platzner M. Zippy – A coarse-grained reconfigurable array with support for hardware virtualization. In: Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP). IEEE Computer Society; 2005:213-218. doi:10.1109/ASAP.2005.69
LibreCat: /record/2411
DOI: 10.1109/ASAP.2005.69

Enzler R, Plessl C, Platzner M. System-level performance evaluation of reconfigurable processors. Microprocessors and Microsystems. 2005;29(2-3):63-73. doi:10.1016/j.micpro.2004.06.004
LibreCat: /record/2412
DOI: 10.1016/j.micpro.2004.06.004

Plessl C, Platzner M. Virtualization of Hardware – Introduction and Survey. In: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press; 2004:63-69.
LibreCat: /record/2415

Plessl C, Platzner M. TKDM – A Reconfigurable Co-processor in a PC’s Memory Slot. In: Proc. Int. Conf. on Field Programmable Technology (ICFPT). IEEE Computer Society; 2003:252-259. doi:10.1109/FPT.2003.1275755
LibreCat: /record/2418
DOI: 10.1109/FPT.2003.1275755

Plessl C, Enzler R, Walder H, et al. The Case for Reconfigurable Hardware in Wearable Computing. Personal and Ubiquitous Computing. 2003;7(5):299-308. doi:10.1007/s00779-003-0243-x
LibreCat: /record/2419
DOI: 10.1007/s00779-003-0243-x

Plessl C, Platzner M. Instance-Specific Accelerators for Minimum Covering. Journal of Supercomputing. 2003;26(2):109-129. doi:10.1023/a:1024443416592
LibreCat: /record/2420
DOI: 10.1023/a:1024443416592

Enzler R, Plessl C, Platzner M. Virtualizing Hardware with Multi-Context Reconfigurable Arrays. In: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL). Vol 2778. Lecture Notes in Computer Science (LNCS). Springer; 2003:151-160. doi:10.1007/b12007
LibreCat: /record/2421
DOI: 10.1007/b12007

Enzler R, Plessl C, Platzner M. Co-simulation of a Hybrid Multi-Context Architecture. In: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press; 2003:174-180.
LibreCat: /record/2422

Plessl C, Enzler R, Walder H, Beutel J, Platzner M, Thiele L. Reconfigurable Hardware in Wearable Computing Nodes. In: Proc. Int. Symp. on Wearable Computers (ISWC). IEEE Computer Society; 2002:215-222. doi:10.1109/ISWC.2002.1167250
LibreCat: /record/2423
DOI: 10.1109/ISWC.2002.1167250