Lass, Michael. Localization and Analysis of Code Paths Suitable for Acceleration Using Approximate Computing. Paderborn University, 2015.

Jenert, Tobias, and Taiga Brahm. How Do They Find Their Place? A Longitudinal Study of Management Students’ Attitudes and Motivations During Their First Year at Business School. 2015.

Funke, Lukas. An LLVM Based Toolchain for Transparent Acceleration of Digital Image Processing Applications Using FPGA Overlay Architectures. Universität Paderborn, 2015.

Löcke, Thomas. Instance-Specific Computing in Hard- and Software for Faster Solving of Complex Problems. Universität Paderborn, 2015.

Wallaschek, Felix. Accelerating Programmable Logic Controllers with the Use of FPGAs. Universität Paderborn, 2015.

Beisel, Tobias. Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing. Logos Verlag Berlin GmbH, 2015.

Kenter, Tobias, et al. “Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study.”10.1155/2015/859425__International Journal of Reconfigurable Computing (IJRC), vol. 2015, 859425, Hindawi, 2015, doi:10.1155/2015/859425.

Damschen, Marvin, and Christian Plessl. “Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores.” Proceedings of the 5th International Workshop on Adaptive Self-Tuning Computing Systems (ADAPT), 2015.

Schumacher, Jörn, et al. “Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm.”10.1145/2675743.2771824__Proc. Int. Conf. on Distributed Event-Based Systems (DEBS), ACM, 2015, doi:10.1145/2675743.2771824.

Plessl, Christian, et al. “Aktuelles Schlagwort: Approximate Computing.”10.1007/s00287-015-0911-z__Informatik Spektrum, no. 5, Springer, 2015, pp. 396–99, doi:10.1007/s00287-015-0911-z.

Damschen, Marvin, et al. “Transparent Offloading of Computational Hotspots from Binary Code to Xeon Phi.”10.7873/DATE.2015.1124__Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE), EDA Consortium / IEEE, 2015, pp. 1078–83, doi:10.7873/DATE.2015.1124.

Anderson, J., et al. “FELIX: A High-Throughput Network Approach for Interfacing to Front End Electronics for ATLAS Upgrades.”10.1088/1742-6596/664/8/082050__Journal of Physics: Conference Series, vol. 664, 082050, IOP Publishing, 2015, doi:10.1088/1742-6596/664/8/082050.

Platzner, Marco, and Christian Plessl. “Verschiebungen an der Grenze zwischen Hardware und Software.” Logiken strukturbildender Prozesse: Automatismen, edited by Jörn Künsemöller et al., Wilhelm Fink, 2014, pp. 123–44.

Kenter, Tobias, et al. “Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer.”10.1007/978-3-319-05960-0_13__Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC), vol. 8405, Springer International Publishing, 2014, pp. 144–55, doi:10.1007/978-3-319-05960-0_13.

Agne, Andreas, et al. “Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators.”10.1016/j.micpro.2013.12.001__Microprocessors and Microsystems, vol. 38, no. 8, Part B, Elsevier, 2014, pp. 911–19, doi:10.1016/j.micpro.2013.12.001.

Riebler, Heinrich, et al. “Reconstructing AES Key Schedules from Decayed Memory with FPGAs.”10.1109/FCCM.2014.67__Proceedings of Field-Programmable Custom Computing Machines (FCCM), IEEE, 2014, pp. 222–29, doi:10.1109/FCCM.2014.67.

Agne, Andreas, et al. “Self-Awareness as a Model for Designing and Operating Heterogeneous Multicores.”10.1145/2617596__ACM Transactions on Reconfigurable Technology and Systems (TRETS), vol. 7, no. 2, 13, ACM, 2014, doi:10.1145/2617596.

Agne, Andreas, et al. “ReconOS - An Operating System Approach for Reconfigurable Computing.”10.1109/MM.2013.110__IEEE Micro, vol. 34, no. 1, IEEE, 2014, pp. 60–71, doi:10.1109/MM.2013.110.

C. Durelli, Gianluca, et al. “Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach.”10.1109/ISPA.2014.27__Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA), IEEE, 2014, pp. 142–49, doi:10.1109/ISPA.2014.27.

Vaz, Gavin Francis, et al. “Deferring Accelerator Offloading Decisions to Application Runtime.”10.1109/ReConFig.2014.7032509__Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2014, pp. 1–8, doi:10.1109/ReConFig.2014.7032509.

Kenter, Tobias, et al. “Kernel-Centric Acceleration of High Accuracy Stereo-Matching.”10.1109/ReConFig.2014.7032535__Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2014, pp. 1–8, doi:10.1109/ReConFig.2014.7032535.

C. Durelli, Gianluca, et al. “SAVE: Towards Efficient Resource Management in Heterogeneous System Architectures.”10.1007/978-3-319-05960-0_38__Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC), Springer, 2014, doi:10.1007/978-3-319-05960-0_38.

Giefers, Heiner, et al. “Accelerating Finite Difference Time Domain Simulations with Reconfigurable Dataflow Computers.”10.1145/2641361.2641372__ACM SIGARCH Computer Architecture News, vol. 41, no. 5, ACM, 2014, pp. 65–70, doi:10.1145/2641361.2641372.

Riebler, Heinrich. Identifikation und Wiederherstellung von kryptographischen Schlüsseln mit FPGAs. Universität Paderborn, 2013.

Riebler, Heinrich, et al. “FPGA-Accelerated Key Search for Cold-Boot Attacks against AES.”10.1109/FPT.2013.6718394__Proceedings of the International Conference on Field-Programmable Technology (FPT), IEEE, 2013, pp. 386–89, doi:10.1109/FPT.2013.6718394.

Happe, Markus, et al. “On-The-Fly Computing: A Novel Paradigm for Individualized IT Services.”10.1109/ISORC.2013.6913232__Proceedings of the 9th IEEE Workshop on Software Technology for Future Embedded and Ubiquitous Systems (SEUS), IEEE, 2013, doi:10.1109/ISORC.2013.6913232.

Suess, Tim, et al. “Parallel Macro Pipelining on the Intel SCC Many-Core Computer.”10.1109/IPDPSW.2013.136__Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW), IEEE Computer Society, 2013, pp. 64–73, doi:10.1109/IPDPSW.2013.136.

Grunzke, Richard, et al. “A Data Driven Science Gateway for Computational Workflows.” Proc. UNICORE Summit, 2012.

Plessl, Christian, et al. Programming Models for Reconfigurable Heterogeneous Multi-Cores. Awareness Magazine, 2012.

Meyer, Björn, et al. “Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?”10.1109/FPL.2012.6339370__Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), IEEE, 2012, pp. 189–96, doi:10.1109/FPL.2012.6339370.

Schumacher, Tobias, et al. “IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators.”10.1016/j.micpro.2011.04.002__Microprocessors and Microsystems, vol. 36, no. 2, 2012, pp. 110–26, doi:10.1016/j.micpro.2011.04.002.

Happe, Markus, et al. “Eight Ways to Put Your FPGA on Fire – A Systematic Study of Heat Generators.”10.1109/ReConFig.2012.6416745__Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), IEEE, 2012, pp. 1–8, doi:10.1109/ReConFig.2012.6416745.

Kenter, Tobias, et al. “Pragma Based Parallelization - Trading Hardware Efficiency for Ease of Use?”10.1109/ReConFig.2012.6416773__Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2012, pp. 1–8, doi:10.1109/ReConFig.2012.6416773.

Happe, Markus, et al. “Hardware/Software Platform for Self-Aware Compute Nodes.” Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS), 2012, pp. 8–9.

Barrio, Pablo, et al. “Turning Control Flow Graphs into Function Calls: Code Generation for Heterogeneous Architectures.”10.1109/HPCSim.2012.6266973__Proceedings of the International Conference on High Performance Computing and Simulation (HPCS), IEEE, 2012, pp. 559–65, doi:10.1109/HPCSim.2012.6266973.

Rüthing, Christoph, et al. “Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs.”10.1109/FPL.2012.6339370__Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), IEEE, 2012, pp. 559–62, doi:10.1109/FPL.2012.6339370.

Beisel, Tobias, et al. “Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux.” Proc. Workshop on Computer Architecture and Operating System Co-Design (CAOS), 2012.

Grad, Mariusz, and Christian Plessl. “On the Feasibility and Limitations of Just-In-Time Instruction Set Extension for FPGA-Based Reconfigurable Processors.”10.1155/2012/418315__Int. Journal of Reconfigurable Computing (IJRC), Hindawi Publishing Corp., 2012, doi:10.1155/2012/418315.

Kenter, Tobias, et al. “Estimation and Partitioning for CPU-Accelerator Architectures.” Intel European Research and Innovation Conference, 2011.

Plessl, Christian, and Marco Platzner. “Hardware Virtualization on Dynamically Reconfigurable Embedded Processors.”10.4018/978-1-60960-086-0__Reconfigurable Embedded Control Systems: Applications for Flexibility and Agility, edited by Mohamed Khalgui and Hans-Michael Hanisch, IGI Global, 2011, doi:10.4018/978-1-60960-086-0.

Sekanina, Lukas, et al. “Evolution of Electronic Circuits.” Cartesian Genetic Programming, Springer Berlin Heidelberg, 2011, pp. 125–79.

Meyer, Björn, et al. “Transformation of Scientific Algorithms to Parallel Computing Code: Subdomain Support in a MPI-Multi-GPU Backend.”10.1109/SAAHPC.2011.12__Symp. on Application Accelerators in High Performance Computing (SAAHPC), IEEE Computer Society, 2011, pp. 60–63, doi:10.1109/SAAHPC.2011.12.

Beisel, Tobias, et al. “Cooperative Multitasking for Heterogeneous Accelerators in the Linux Completely Fair Scheduler.”10.1109/ASAP.2011.6043273__Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), IEEE Computer Society, 2011, pp. 223–26, doi:10.1109/ASAP.2011.6043273.

Happe, Markus, et al. “Measuring and Predicting Temperature Distributions on FPGAs at Run-Time.”10.1109/ReConFig.2011.59__Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig), IEEE, 2011, pp. 55–60, doi:10.1109/ReConFig.2011.59.

Kenter, Tobias, et al. “Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures.”10.1145/1950413.1950448__Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA), ACM, 2011, pp. 177–80, doi:10.1145/1950413.1950448.

Schumacher, Tobias, et al. “FPGA Acceleration of Communication-Bound Streaming Applications: Architecture Modeling and a 3D Image Compositing Case Study.”10.1155/2011/760954__Int. Journal of Recon- Figurable Computing (IJRC), Hindawi Publishing Corp., 2011, doi:10.1155/2011/760954.

Grad, Mariusz, and Christian Plessl. “Just-in-Time Instruction Set Extension – Feasibility and Limitations for an FPGA-Based Reconfigurable ASIP Architecture.”10.1109/IPDPS.2011.153__Proc. Reconfigurable Architectures Workshop (RAW), IEEE Computer Society, 2011, pp. 278–85, doi:10.1109/IPDPS.2011.153.

Lübbers, Enno, et al. “Towards Adaptive Networking for Embedded Devices Based on Reconfigurable Hardware.” Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2010, pp. 225–31.

Grad, Mariusz, and Christian Plessl. “Pruning the Design Space for Just-In-Time Processor Customization.”10.1109/ReConFig.2010.19__Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), IEEE Computer Society, 2010, pp. 67–72, doi:10.1109/ReConFig.2010.19.

Grad, Mariusz, and Christian Plessl. “An Open Source Circuit Library with Benchmarking Facilities.” Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2010, pp. 144–50.