Architectural Low-Power Design Using Transaction-Based System Modeling and Simulation
F. Mischkalla, W. Müller, in: Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV), IEEE, Greece, 2014.

 Switchable slow wave transmission line in 130 nm SiGe technology at 115 GHz for phase detection based biosensors
J. Wessel, K. Schmalz, C. Scheytt, C. Meliani, in: Microwave Symposium (IMS), 2014 IEEE MTT-S International, IEEE, Tampa, FL, USA, 2014, pp. 1–3.

A 7 GHz biosensor for permittivity change with enhanced sensitivity through phase compensation
J. Wessel, K. Schmalz, C. Scheytt, C. Meliani, B. Cahill, in: European Microwave Conference (EuMC), IEEE, Fiera, Roma, 2014, pp. 699–702.

Wireless 100 Gb/s: PHY layer Overview and Challenges in THz freqency band
R. Kraemer, A. Wolf, C. Scheytt, I. Kallfass, K. KrishneGowda, in: 2014 IEEE 15th Annual IEEE Wireless and Microwave Technology Conference (WAMICON), IEEE, Marriott Waterside Hotel and Marina Tampa, FL, USA, 2014.

Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU
B. Koppelmann, B. Messidat, M. Becker, C. Kuznik, W. Müller, C. Scheytt, Design and Verification Conference (DVCON EUROPE) (2014).

Verific-MM: Systematized Verification Metrics Generation with UCIS for Improved Automation on Verification Closure
C. Kuznik, W. Müller, Design, Automation and Test in Europe DATE, University Booth, Dresden (2014).

System-on-Chip Design für Funkfrequenzen oberhalb von 100 GHz-Herausforderungen und potenzielle Anwendungen
C. Scheytt, in: Analog 2014,14. Fachtagung Der Gesellschaft Für Mikroelektronik, Mikrosystemtechnik Und Feinwerktechnik Des VDE Und VDI, 2014.

A -Band Four-Element Butler Matrix in 0.13 µm SiGe BiCMOS Technology
M. Elkhouly, Y. Mao, C. Meliani, C. Scheytt, F. Ellinger, IEEE JOURNAL OF SOLID-STATE CIRCUITS 49 (2014).

Safety Evaluation of Automotive Electronics Using Virtual Prototypes: State of the Art and Research Challenges
J.-H. Oetjens, M. Becker, C. Kuznik, W. Müller, N. Bannow, O. Brinkmann, A. Burger, M. Chaari, S. Chakraborty, R. Drechsler, W. Ecker, K. Grüttner, T. Kruse, H.M. Le, M. Mauderer, D. Mueller-Gritschneider, F. Poppen, H. Post, Se. Reiter, W. Rosenstiel, S. Roth, U. Schlichtmann, A. Von Schwerin, B.A. Tabacaru, A. Viehl, in: Design Automation Conference (DAC), 2014.

mm-Wellen- und Electronic-Photonic System-on-Chip Design
C. Scheytt, in: Fakultätskolloquium Der Fakultät Für Elektrotechnik Und Informationstechnik, Institut für Technologie, Karlsruhe, 2014.

Architectural Low-Power Design Using Transaction-Based System Simulation
F. Mischkalla, W. Müller, in: Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV), IEEE, 2014.

Source code annotated memory leak detection for soft real time embedded systems with resource constraints
M. tech. M.M. Joy, W. Müller, F.-J. Rammig, in: 12th IEEE International Conference on Embedded Computing, 2014.

Advanced SoC Virtual Prototyping for System-Level Power Planning and Validation
F. Mischkalla, W. Müller, in: PATMOS 2014, Palma de Mallorca, Spain, 2014.

Fault Effect Modeling in a Heterogeneous SystemC Based Virtual Platform Framework for Cyber Physical Systems
M. Becker, C. Kuznik, W. Müller, in: IEEE, Berlin, 2014.

An Assisted Single Source Verification Metric Model Code Generation Methodology
C. Kuznik, W. Müller, G.B. Defo, in: San Francisco, USA, 2014.

Modellierung effizienter Stresstest-Umgebungen für virtuelle Prototypen mit SVM
C. Kuznik, W. Müller, in: 26. ITG / GI / GMM Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen, 2014.

Semi-automatische Generierung von Überdeckungsmetriken mittels methodischer Verikationsplan Verarbeitung
C. Kuznik, B.G. Defo, W. Müller, in: 17. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV 2014) , 2014.

An Assisted Single Source Verification Metric Model Code Generation Methodology
C. Kuznik, B.G. Defo, W. Müller, Electronic System Level Synthesis Conference (ESLSyn) (2014).

Design and Measurement Techniques for an 80 Gb/s 1-Tap Decision Feedback Equalizer
A. Awny, L. Möller, J. Junio, C. Scheytt, A. Thiede, IEEE JOURNAL OF SOLID-STATE CIRCUITS Vol.49 (2014) 452–470.

Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU
B. Koppelmann, B. Messidat, M. Becker, W. Müller, J.C. Scheytt, in: Proceedings of the Design and Verification Conference Europe (DVCON Europe), München, 2014.