Regret analysis for performance metrics in multi-label classification: The case of Hamming and subset zero-one loss
K. Dembczynski, W. Waegeman, W. Cheng, E. Hüllermeier, in: In Proceedings ECML/PKDD-2010, European Conference on Machine Learning and Principles and Practice of Knowledge Discovery in Databases, ,Bareclona, Spain, 2010.
LibreCat: /record/13593

Predicting partial orders: Ranking with abstention
W. Cheng, M. Rademaker, B. De Beats, E. Hüllermeier, in: In Proceedings ECML/PKDD-2010, European Conference on Machine Learning and Principles and Practice of Knowledge Discovery in Databases, ,Bareclona, Spain, 2010.
LibreCat: /record/13594

Uncertainty in clustering and classification 
E. Hüllermeier, in: In Proceedings SUM 2010, International Conference on Scalable Uncertainty Management , Springer, 2010, pp. 16–19.
LibreCat: /record/13597

A Triple Hybrid Interconnect for Many-Cores: Reconfigurable Mesh, NoC and Barrier
H. Giefers, M. Platzner, in: Proceedings of the 20th International Conference on Field Programmable Logic and Applications (FPL), IEEE, 2010.
LibreCat: /record/13640

Engineering Self-Coordinating Software Intensive Systems
W. Schäfer, M. Birattari, J. Blömer, M. Dorigo, G. Engels, R. O’Grady, M. Platzner, F.-J. Rammig, W. Reif, A. Trächtler, in: Proceedings of the Foundations of Software Engineering (FSE) and NITR &; D/SPD Working Conference on the Future of Software Engineering Research (FoSER), 2010, pp. 321–324.
LibreCat: /record/13641

A Self-Reconfigurable Lightweight Interconnect for Scalable Processor Fabrics
H. Giefers, M. Platzner, in: Proceedings of the 10th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2010.
LibreCat: /record/13642

Closing the Gap between UML-based Modeling and Simulation of Combined HW/SW Systems
F. Mischkalla, D. He, W. Müller, in: Proceedings of DATE’10, IEEE, Dresden, 2010.
LibreCat: /record/37007
DOI: 10.1109/DATE.2010.5456990

Assertion-Based Verification of RTOS Properties
M.F.S. Oliveira, H. Zabel, W. Müller, in: Proceedings of DATE’10, IEEE, Dresden, 2010.
LibreCat: /record/37009
DOI: 10.1109/DATE.2010.5457130

Timing Modeling and Analysis for AUTOSAR-Based Software Development - A Case Study
K. Klobedanz, C. Kuznik, A. Thuy, W. Müller, in: Proceedings of DATE’10, Dresden, IEEE, Dresden, 2010.
LibreCat: /record/37011
DOI: 10.1109/DATE.2010.5457125

A Systematic Approach to Combined HW/SW System Test
A. Krupp, W. Müller, in: Proceedings of DATE’10, IEEE, Dresden, 2010.
LibreCat: /record/37037
DOI: 10.1109/DATE.2010.5457186

RTOS-Aware Refinement for TLM2.0-based HW/SW Design
M. Becker, G. Di Guglielmo, F. Fummi, W. Müller, G. Pravadelli, T. Xie, in: Proceedings of DATE’10, IEEE, Dresden, 2010.
LibreCat: /record/37040
DOI: 10.1109/DATE.2010.5456965

A Mixed Level Simulation Environment for Stepwise RTOS Software Refinement
M. Becker, H. Zabel, W. Müller, in: L. Kleinjohann, B. Kleinjohann (Eds.), Springer Verlag, Dordrecht, 2010.
LibreCat: /record/37046
DOI: 10.1007/978-3-642-15234-4_15

Task Migration for Fault-Tolerant FlexRay Networks
K. Klobedanz, G.B. Defo, H. Zabel, W. Müller, Y. Zhi, in: L. Kleinjohann, B. Kleinjohann (Eds.), Springer Verlag, Dordrecht, 2010.
LibreCat: /record/37044
DOI: 10.1007/978-3-642-15234-4_7

A UML Profile for SysML-Based Comodeling for Embedded Systems Simulation and Synthesis
F. Mischkalla, W. Müller, D. He, in: Proceedings of the M-BED Workshop, Dresden, 2010.
LibreCat: /record/37042

Eine strukturierte Methode zur Generierung von SystemVerilog-Testumgebungen aus textuellen Anforderungsbeschreibungen
A. Bol, W. Müller, A. Krupp, in: Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV), Dresden, 2010.
LibreCat: /record/37043

The SATURN Approach to SysML-based HW/SW Codesign
W. Müller, D. He, F. Mischkalla, A. Wegele, A. Larkham, P. Whiston, P. Penil, E. Villar, N. Mitas, D. Kritharidis, F. Azcarate, M. Carballeda, in: Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010.
LibreCat: /record/37050
DOI: 10.1007/978-94-007-1488-5_9

Generation of Executable Testbenches from Natural Language Requirement Specifications for Embedded Real-Time Systems
W. Müller, A. Bol, A. Krupp, O. Lundkvist, in: L. Kleinjohann, B. Kleinjohann (Eds.), Springer Verlag, Dordrecht, 2010.
LibreCat: /record/37048
DOI: 10.1007/978-3-642-15234-4_9

Mutation-Analysis Directed Constrained Random Verification
T. Xie, F. Letombe, W. Müller, in: L. Kleinjohann, B. Kleinjohann (Eds.), Springer Verlag, Dordrecht, 2010.
LibreCat: /record/37049

An Eclipse-based Framework for the IP-XACT-enabled Assembly of Mixed-Level IPs
T. Xie, G.B. Defo, W. Müller, in: Paris, 2010.
LibreCat: /record/37051

Verification of a CAN Bus Model in SystemC with Functional Coverage
G.B. Defo, W. Müller, C. Kuznik, in: Proceedings of SIES 2010, IEEE,  Trento, Italy, 2010.
LibreCat: /record/37057
DOI: 10.1109/SIES.2010.5551379