Wiersema T. Guaranteeing Properties of Reconfigurable Hardware Circuits with Proof-Carrying Hardware. Paderborn University; 2021.
LibreCat: /record/26746

Lienen C, Platzner M. Design of Distributed Reconfigurable Robotics Systems with ReconROS. ACM Transactions on Reconfigurable Technology and Systems. Published online 2021:1-20. doi:10.1145/3494571
LibreCat: /record/29150
DOI: 10.1145/3494571

Kashikar C. A Comparison of Machine Learning Techniques for the On-Line Characterization of Tasks Executed on Heterogeneous Compute Nodes. Paderborn University; 2021.
LibreCat: /record/29151

Awais M, Ghasemzadeh Mohammadi H, Platzner M. LDAX: A Learning-based Fast Design Space Exploration Framework for Approximate Circuit Synthesis. In: Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI) 2021. ACM; 2021:27-32. doi:https://doi.org/10.1145/3453688.3461506
LibreCat: /record/21610
DOI: https://doi.org/10.1145/3453688.3461506

Rehnen JW. Decomposition of Arithmetic Components for the Approximate Circuit Synthesis with EvoApproxLib.; 2021.
LibreCat: /record/22216

Awais M, Platzner M. MCTS-Based Synthesis Towards Efficient Approximate Accelerators. In: Proceedings of IEEE Computer Society Annual Symposium on VLSI. IEEE; 2021:384-389.
LibreCat: /record/22309

Brede M. Implementation and Profiling of XCS in the Context of Embedded Systems. Paderborn: Paderborn University; 2021.
LibreCat: /record/22483

Witschen LM, Wiersema T, Raeisi Nafchi M, Bockhorn A, Platzner M. Timing Optimization for Virtual FPGA Configurations. In: Hannig F, Derrien S, Diniz P, Chillet D, eds. Proceedings of International Symposium on Applied Reconfigurable Computing (ARC’21). Reconfigurable Computing: Architectures, Tools, and Applications. Springer Lecture Notes in Computer Science. doi:10.1007/978-3-030-79025-7_4
LibreCat: /record/21953
DOI: 10.1007/978-3-030-79025-7_4

Boschmann A, Neuhaus D, Vogt S, Kaltschmidt C, Platzner M, Dosen S. Immersive augmented reality system for the training of pattern classification control with a myoelectric prosthesis. Journal of NeuroEngineering and Rehabilitation. 2021;18(1). doi:10.1186/s12984-021-00822-6
LibreCat: /record/30906
DOI: 10.1186/s12984-021-00822-6

Rodriguez A, Otero A, Platzner M, De la Torre E. Exploiting Hardware-Based Data-Parallel and Multithreading Models for Smart Edge Computing in Reconfigurable FPGAs. IEEE Transactions on Computers. Published online 2021:1-1. doi:10.1109/tc.2021.3107196
LibreCat: /record/30907
DOI: 10.1109/tc.2021.3107196

Hansmeier T. Self-aware Operation of Heterogeneous Compute Nodes using the Learning Classifier System XCS. In: HEART ’21: Proceedings of the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies. Association for Computing Machinery (ACM); 2021. doi:10.1145/3468044.3468055
LibreCat: /record/29137
DOI: 10.1145/3468044.3468055

Sheikh MA. Design and Implementation of a ReconROS-Based Obstacle Avoidance System. Paderborn University; 2021.
LibreCat: /record/29540

Lienen C, Platzner M. Design of Distributed Reconfigurable Robotics Systems with ReconROS. arXiv:210707208. Published online 2021.
LibreCat: /record/22764

Hansmeier T, Platzner M. An Experimental Comparison of Explore/Exploit Strategies for the Learning Classifier System XCS. In: GECCO ’21: Proceedings of the Genetic and Evolutionary Computation Conference Companion. Association for Computing Machinery (ACM); 2021:1639–1647. doi:10.1145/3449726.3463159
LibreCat: /record/21813
DOI: 10.1145/3449726.3463159

Jakobs M-C, Pauck F, Platzner M, Wehrheim H, Wiersema T. Software/Hardware Co-Verification for Custom Instruction Set Processors. IEEE Access. Published online 2021. doi:10.1109/ACCESS.2021.3131213
LibreCat: /record/27841
DOI: 10.1109/ACCESS.2021.3131213

Ahmed QA. Hardware Trojans in Reconfigurable Computing. In: 2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SoC). ; 2021. doi:10.1109/vlsi-soc53125.2021.9606974
LibreCat: /record/29138
DOI: 10.1109/vlsi-soc53125.2021.9606974

Ahmed QA, Wiersema T, Platzner M. Malicious Routing: Circumventing Bitstream-level Verification for FPGAs. In: 2021 Design, Automation &; Test in Europe Conference &; Exhibition (DATE). 2021 Design, Automation and Test in Europe Conference (DATE); 2021. doi:10.23919/DATE51398.2021.9474026
LibreCat: /record/20681
DOI: 10.23919/DATE51398.2021.9474026

Clausing L. ReconO: High-Performance Embedded Computing for Industrial Analytics on a Reconfigurable System-on-Chip. In: Proceedings of the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies. ACM; 2021. doi:10.1145/3468044.3468056
LibreCat: /record/30909
DOI: 10.1145/3468044.3468056

Ghasemzadeh Mohammadi H, Jentzsch F, Kuschel M, et al. FLight: FPGA Acceleration of Lightweight DNN Model Inference in Industrial Analytics. In: https://doi.org/10.1007/978-3-030-93736-2_27__Machine Learning and Principles and Practice of Knowledge Discovery in Databases. Springer; 2021. doi:https://doi.org/10.1007/978-3-030-93736-2_27
LibreCat: /record/30908
DOI: https://doi.org/10.1007/978-3-030-93736-2_27