T. Wiersema, Guaranteeing Properties of Reconfigurable Hardware Circuits with Proof-Carrying Hardware. Paderborn: Paderborn University, 2021.
LibreCat: /record/26746

C. Lienen and M. Platzner, “Design of Distributed Reconfigurable Robotics Systems with ReconROS,”10.1145/3494571__ACM Transactions on Reconfigurable Technology and Systems, pp. 1–20, 2021, doi:10.1145/3494571 .
LibreCat: /record/29150
DOI: 10.1145/3494571

C. Kashikar, A Comparison of Machine Learning Techniques for the On-line Characterization of Tasks Executed on Heterogeneous Compute Nodes. Paderborn: Paderborn University, 2021.
LibreCat: /record/29151

M. Awais, H. Ghasemzadeh Mohammadi, and M. Platzner, “LDAX: A Learning-based Fast Design Space Exploration Framework for Approximate Circuit Synthesis,” in Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI) 2021, Virtual, 2021, pp. 27–32.
LibreCat: /record/21610
DOI: https://doi.org/10.1145/3453688.3461506

J. W. Rehnen, Decomposition of Arithmetic Components for the Approximate Circuit Synthesis with EvoApproxLib. 2021.
LibreCat: /record/22216

M. Awais and M. Platzner, “MCTS-Based Synthesis Towards Efficient Approximate Accelerators,” in Proceedings of IEEE Computer Society Annual Symposium on VLSI, Tampa, Florida USA (Virtual), 2021, pp. 384–389.
LibreCat: /record/22309

M. Brede, Implementation and Profiling of XCS in the Context of Embedded Systems. Paderborn: Paderborn University, 2021.
LibreCat: /record/22483

L. M. Witschen, T. Wiersema, M. Raeisi Nafchi, A. Bockhorn, and M. Platzner, “Timing Optimization for Virtual FPGA Configurations,”10.1007/978-3-030-79025-7_4__in Proceedings of International Symposium on Applied Reconfigurable Computing (ARC’21), Virtual conference, doi:10.1007/978-3-030-79025-7_4 .
LibreCat: /record/21953
DOI: 10.1007/978-3-030-79025-7_4

A. Boschmann, D. Neuhaus, S. Vogt, C. Kaltschmidt, M. Platzner, and S. Dosen, “Immersive augmented reality system for the training of pattern classification control with a myoelectric prosthesis,”10.1186/s12984-021-00822-6__Journal of NeuroEngineering and Rehabilitation, vol. 18, no. 1, Art. no. 25, 2021, doi:10.1186/s12984-021-00822-6 .
LibreCat: /record/30906
DOI: 10.1186/s12984-021-00822-6

A. Rodriguez, A. Otero, M. Platzner, and E. De la Torre, “Exploiting Hardware-Based Data-Parallel and Multithreading Models for Smart Edge Computing in Reconfigurable FPGAs,”10.1109/tc.2021.3107196__IEEE Transactions on Computers, pp. 1–1, 2021, doi:10.1109/tc.2021.3107196 .
LibreCat: /record/30907
DOI: 10.1109/tc.2021.3107196

T. Hansmeier, “Self-aware Operation of Heterogeneous Compute Nodes using the Learning Classifier System XCS,”10.1145/3468044.3468055__presented at the International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART ’21), Online, 2021, doi:10.1145/3468044.3468055 .
LibreCat: /record/29137
DOI: 10.1145/3468044.3468055

M. A. Sheikh, Design and Implementation of a ReconROS-based Obstacle Avoidance System. Paderborn University, 2021.
LibreCat: /record/29540

C. Lienen and M. Platzner, “Design of Distributed Reconfigurable Robotics Systems with ReconROS,” arXiv:2107.07208. 2021.
LibreCat: /record/22764

T. Hansmeier and M. Platzner, “An Experimental Comparison of Explore/Exploit Strategies for the Learning Classifier System XCS,”10.1145/3449726.3463159__in GECCO ’21: Proceedings of the Genetic and Evolutionary Computation Conference Companion, Lille, France, 2021, pp. 1639–1647, doi:10.1145/3449726.3463159 .
LibreCat: /record/21813
DOI: 10.1145/3449726.3463159

M.-C. Jakobs, F. Pauck, M. Platzner, H. Wehrheim, and T. Wiersema, “Software/Hardware Co-Verification for Custom Instruction Set Processors,”10.1109/ACCESS.2021.3131213__IEEE Access, 2021, doi:10.1109/ACCESS.2021.3131213 .
LibreCat: /record/27841
DOI: 10.1109/ACCESS.2021.3131213

Q. A. Ahmed, “Hardware Trojans in Reconfigurable Computing,”10.1109/vlsi-soc53125.2021.9606974__2021, doi:10.1109/vlsi-soc53125.2021.9606974 .
LibreCat: /record/29138
DOI: 10.1109/vlsi-soc53125.2021.9606974

Q. A. Ahmed, T. Wiersema, and M. Platzner, “Malicious Routing: Circumventing Bitstream-level Verification for FPGAs,”10.23919/DATE51398.2021.9474026__presented at the Design, Automation and Test in Europe Conference (DATE’21), Alpexpo | Grenoble, France, 2021, doi:10.23919/DATE51398.2021.9474026 .
LibreCat: /record/20681
DOI: 10.23919/DATE51398.2021.9474026

L. Clausing, “ReconO: High-Performance Embedded Computing for Industrial Analytics on a Reconfigurable System-on-Chip,”10.1145/3468044.3468056__2021, doi:10.1145/3468044.3468056 .
LibreCat: /record/30909
DOI: 10.1145/3468044.3468056

H. Ghasemzadeh Mohammadi et al., “FLight: FPGA Acceleration of Lightweight DNN Model Inference in Industrial Analytics,”https://doi.org/10.1007/978-3-030-93736-2_27__2021, doi:https://doi.org/10.1007/978-3-030-93736-2_27 .
LibreCat: /record/30908
DOI: https://doi.org/10.1007/978-3-030-93736-2_27