Hardware Acceleration of Mechatronic Controllers on a Zynq Platform FPGA
B. Koch, Hardware Acceleration of Mechatronic Controllers on a Zynq Platform FPGA, Paderborn University, 2014.

Advanced AES-key recovery from decayed RAM using multi-threading and FPGAs
R. Mittendorf, Advanced AES-Key Recovery from Decayed RAM Using Multi-Threading and FPGAs, Paderborn University, 2014.

The Xilinx Zynq Architecture as a Platform for Reconfigurable Heterogeneous Multi-Cores
C. Rüthing, The Xilinx Zynq Architecture as a Platform for Reconfigurable Heterogeneous Multi-Cores, Paderborn University, 2014.

Parallel Monte-Carlo Tree Search for HPC Systems and its Application to Computer Go
L. Schäfers, Parallel Monte-Carlo Tree Search for HPC Systems and Its Application to Computer Go, Logos Verlag Berlin GmbH, Berlin, 2014.

Optimizing the Generator Start-up Sequence After a Power System Blackout
C. Shen, P. Kaufmann, M. Braun, in: IEEE Power and Energy Society General Meeting (IEEE GM), 2014.

A New Distribution Network Reconfiguration and Restoration Path Selection Algorithm
C. Shen, P. Kaufmann, M. Braun, in: Power Systems Computation Conference (PSCC), IEEE, 2014.

Multithreaded Parallelization of Mechatronic Controllers on a Zynq Platform FPGA
S. Surmund, Multithreaded Parallelization of Mechatronic Controllers on a Zynq Platform FPGA, Paderborn University, 2014.

Applications of Evolutionary Computation - 17th European Conference, EvoApplications
A. I. Esparcia-Alc\rquote azar, A.E. Eiben, A. Agapitos, A. Sim\'7eoes, A. G.B. Tettamanzi, A. Della Cioppa, A. M. Mora, C. Cotta, E. Tarantino, E. Haasdijk, F. Divina, F. Fern\rquote andez de Vega, G. Squillero, I. De Falco, J. Ignacio Hidalgo, K. Sim, K. Glette, M. Zhang, N. Urquhart, P. Burelli, P. Kaufmann, P. Po\'76 s\rquote k, R. Schaefer, R. Drechsler, S. Antipolis, S. Cagnoni, T. Thanh Nguyen, W. S. Bush (editors), Applications of Evolutionary Computation - 17th European Conference, EvoApplications, Springer, Granada, Spain, 2014.

Analytic reliability evaluation for fault-tolerant circuit structures on FPGAs
J. Anwer, M. Platzner, in: IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), IEEE, 2014, pp. 177–184.

Fast process variation analysis in nano-scaled technologies using column-wise sparse parameter selection
H. Ghasemzadeh Mohammadi, P.-E. Gaillardon, M. Yazdani, G. De Micheli, in: 2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), IEEE, 2014, pp. 163–168.