Anwer J, Platzner M. Evaluating fault-tolerance of redundant FPGA structures using Boolean difference calculus. Microprocessors and Microsystems. 2017:160-172. doi:10.1016/j.micpro.2017.06.002
LibreCat: /record/10611
DOI: 10.1016/j.micpro.2017.06.002

Kaltschmidt C. An AR-Based Training and Assessment System for Myoelectrical Prosthetic Control. Paderborn University; 2017.
LibreCat: /record/10613

Boschmann A, Thombansen G, Witschen LM, Wiens A, Platzner M. A Zynq-based dynamically reconfigurable high density myoelectric prosthesis controller. In: Design, Automation and Test in Europe (DATE). ; 2017. doi:10.23919/DATE.2017.7927137
LibreCat: /record/10630
DOI: 10.23919/DATE.2017.7927137

Riaz U. Acceleration of Industrial Analytics Functions on a Platform FPGA. Paderborn University; 2017.
LibreCat: /record/10666

Ho N, Ashraf II, Kaufmann P, Platzner M. Accurate Private/Shared Classification of Memory Accesses: a Run-time Analysis System for the LEON3 Multi-core Processor. In: Proc. Design, Automation and Test in Europe Conf. (DATE). ; 2017. doi:10.23919/DATE.2017.7927096
LibreCat: /record/10672
DOI: 10.23919/DATE.2017.7927096

Ho N, Kaufmann P, Platzner M. Evolvable caches: Optimization of reconfigurable cache mappings for a LEON3/Linux-based multi-core processor. In: 2017 International Conference on Field Programmable Technology (ICFPT). ; 2017:215-218. doi:10.1109/FPT.2017.8280144
LibreCat: /record/10676
DOI: 10.1109/FPT.2017.8280144

Shen C, Kaufmann P, Braun M. Three-Stage Power System Restoration Methodology Considering Renewable Energies. Elsevier International Journal of Electrical Power and Energy Systems (IJEPES). 2017.
LibreCat: /record/10692

Dietrich A. Reconfigurable Cryptographic Services. Paderborn University; 2017.
LibreCat: /record/10708

Shen C, Kaufmann P, Braun M. Fast Network Restoration by Partitioning of Parallel Black Start Zones. The Journal of Engineering. 2017:19pp. doi:10.1049/joe.2017.0032
LibreCat: /record/10740
DOI: 10.1049/joe.2017.0032

Squillero G, Burelli P, M. Mora A, et al. Applications of Evolutionary Computation - 20th European Conference, EvoApplications. Springer; 2017.
LibreCat: /record/10759

Kaufmann P, Kalkreuth R. Parametrizing Cartesian Genetic Programming: An Empirical Study. In: KI 2017: Advances in Artificial Intelligence: 40th Annual German Conference on AI. Springer International Publishing; 2017. doi:10.1007/978-3-319-67190-1_26
LibreCat: /record/10760
DOI: 10.1007/978-3-319-67190-1_26

Kaufmann P, Ho N, Platzner M. Evaluation Methodology for Complex Non-deterministic Functions: A Case Study in Metaheuristic Optimization of Caches. In: Adaptive Hardware and Systems (AHS). IEEE; 2017. doi:10.1109/AHS.2017.8046380
LibreCat: /record/10761
DOI: 10.1109/AHS.2017.8046380

Kaufmann P, Kalkreuth R. An Empirical Study on the Parametrization of Cartesian Genetic Programming. In: Genetic and Evolutionary Computation (GECCO), Compendium. ACM; 2017. doi:10.1145/3067695.3075980
LibreCat: /record/10762
DOI: 10.1145/3067695.3075980

Guettatfi Z, Hübner P, Platzner M, Rinner B. Computational self-awareness as design approach for visual sensor nodes. In: 12th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC). ; 2017:1-8. doi:10.1109/ReCoSoC.2017.8016147
LibreCat: /record/10780
DOI: 10.1109/ReCoSoC.2017.8016147

Ghribi I, Abdallah RB, Khalgui M, Platzner M. I-Codesign: A Codesign Methodology for Reconfigurable Embedded Systems. In: Communications in Computer and Information Science. Cham: Springer ; 2017. doi:10.1007/978-3-319-62569-0_8
LibreCat: /record/14893
DOI: 10.1007/978-3-319-62569-0_8

Wiersema T, Bockhorn A, Platzner M. An Architecture and Design Tool Flow for Embedding a Virtual FPGA into a Reconfigurable System-on-Chip. Computers &; Electrical Engineering. 2016:112--122. doi:10.1016/j.compeleceng.2016.04.005
LibreCat: /record/222
DOI: 10.1016/j.compeleceng.2016.04.005

Boschmann A, Agne A, Witschen L, Thombansen G, Kraus F, Platzner M. FPGA-based acceleration of high density myoelectric signal processing. In: 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE; 2016. doi:10.1109/reconfig.2015.7393312
LibreCat: /record/5812
DOI: 10.1109/reconfig.2015.7393312

Cedric Mertens J. Sprint Diagnostic with RTK-GPS \'26; IMU Sensor Fusion. Paderborn University; 2016.
LibreCat: /record/10612

Nassery AS. Implementation of Bilinear Pairings on Reconfigurable Hardware. Paderborn University; 2016.
LibreCat: /record/10616

Amin O. Acceleration of EMTP for Distribution Networks on Data Flow Machines Using the Latency Insertion Method. Paderborn University; 2016.
LibreCat: /record/10617

Anwer J, Platzner M. Boolean Difference Based Reliability Evaluation of Fault Tolerant Circuit Structures on FPGAs. In: Euromicro Conference on Digital System Design (DSD). ; 2016. doi:10.1109/DSD.2016.35
LibreCat: /record/10622
DOI: 10.1109/DSD.2016.35

Boschmann A, Dosen S, Werner A, Raies A, Farina D. A novel immersive augmented reality system for prosthesis training and assessment. In: Proc. IEEE Int. Conf. Biomed. Health Informatics (BHI). ; 2016.
LibreCat: /record/10631

Graf T, Platzner M. Adaptive playouts for online learning of policies during Monte Carlo Tree Search. Journal Theoretical Computer Science. 2016;644:53-62. doi:10.1016/j.tcs.2016.06.029
LibreCat: /record/10661
DOI: 10.1016/j.tcs.2016.06.029

Horstmann J. Beschleunigte Simulation Elektrischer Stromnetze Mit GPUs. Paderborn University; 2016.
LibreCat: /record/10695

Ma C, Kaufmann P, Töbermann J-C, Braun M. Optimal Generation Dispatch of Distributed Generators Considering Fair Contribution to Grid Voltage Control. Renewable Energy. 2016;87((part 2)):946-953. doi:10.1016/j.renene.2015.07.083
LibreCat: /record/10705
DOI: 10.1016/j.renene.2015.07.083

Makeswaran V. Operating System Support for Reconfigurable Cache. Paderborn University; 2016.
LibreCat: /record/10706

Ibne Ashraf I. Private/Shared Data Classification and Implementation for a Multi-Softcore Platform. Paderborn University; 2016.
LibreCat: /record/10707

Meisner S, Platzner M. Thread Shadowing: On the Effectiveness of Error Detection at the Hardware Thread Level. In: Reconfigurable Computing and FPGAs (ReConFig), 2016 International Conference On. ReConFig. ; 2016:1-8. doi:10.1109/ReConFig.2016.7857193
LibreCat: /record/10712
DOI: 10.1109/ReConFig.2016.7857193

Schmidt M. Konzeption Und Implementierung Einer Digitalen Ansteuerung Für Den Betrieb Einer Elektrischen Sendereinheit Für Induktive Energieübertragung. Paderborn University; 2016.
LibreCat: /record/10755

Squillero G, Burelli P, M. Mora A, et al. Applications of Evolutionary Computation - 19th European Conference, EvoApplications. Vol 9597. Springer; 2016.
LibreCat: /record/10758

Ghribi I, Ben Abdallah R, Khalgui M, Platzner M. RCo-Design: New Visual Environment for Reconfigurable Embedded Systems. In: Proceedings of the 30th European Simulation and Modelling Conference (ESM). ; 2016.
LibreCat: /record/10766

Ghribi I, Ben Abdallah R, Khalgui M, Platzner M. New Co-design Methodology for Real-time Embedded Systems. In: Proceedings of the 11th International Conference on Software Engineering and Applications (ICSOFT-EA). ; 2016:185-195.
LibreCat: /record/10768

Ghasemzadeh Mohammadi H, Gaillardon P-E, De Micheli G. Efficient Statistical Parameter Selection for Nonlinear Modeling of Process/Performance Variation. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2016;PP(99):1-1. doi:10.1109/TCAD.2016.2547908
LibreCat: /record/10769
DOI: 10.1109/TCAD.2016.2547908

Hermansen S. Custom Memory Controller for ReconOS. Paderborn University; 2016.
LibreCat: /record/10781

Lewis PR, Platzner M, Rinner B, Tørresen J, Yao X, eds. Self-Aware Computing Systems: An Engineering Approach. Cham: Springer; 2016. doi:10.1007/978-3-319-39675-0
LibreCat: /record/12972
DOI: 10.1007/978-3-319-39675-0

Boschmann A, Agne A, Witschen LM, Thombansen G, Kraus F, Platzner M. FPGA-based acceleration of high density myoelectric signal processing. In: 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE; 2016. doi:10.1109/reconfig.2015.7393312
LibreCat: /record/15873
DOI: 10.1109/reconfig.2015.7393312

Graf T, Platzner M. Using Deep Convolutional Neural Networks in Monte Carlo Tree Search. In: Computer and Games. ; 2016.
LibreCat: /record/13151

Graf T, Platzner M. Monte-Carlo Simulation Balancing Revisited. In: IEEE Computational Intelligence and Games. ; 2016.
LibreCat: /record/13152

Wiersema T, Platzner M. Verifying Worst-Case Completion Times for Reconfigurable Hardware Modules using Proof-Carrying Hardware. In: Proceedings of the 11th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC 2016). ; 2016:1--8. doi:10.1109/ReCoSoC.2016.7533910
LibreCat: /record/132
DOI: 10.1109/ReCoSoC.2016.7533910

Agne A, Platzner M, Plessl C, Happe M, Lübbers E. ReconOS. In: Koch D, Hannig F, Ziener D, eds. FPGAs for Software Programmers. Springer International Publishing; 2016:227-244. doi:10.1007/978-3-319-26408-0_13
LibreCat: /record/29
DOI: 10.1007/978-3-319-26408-0_13

Agne A, Happe M, Lösch A, Plessl C, Platzner M. Self-aware Compute Nodes. In: Self-Aware Computing Systems. Natural Computing Series (NCS). Springer International Publishing; 2016:145-165. doi:10.1007/978-3-319-39675-0_8
LibreCat: /record/156
DOI: 10.1007/978-3-319-39675-0_8

Lösch A, Beisel T, Kenter T, Plessl C, Platzner M. Performance-centric scheduling with task migration for a heterogeneous compute node in the data center. In: Proceedings of the 2016 Design, Automation &; Test in Europe Conference &; Exhibition (DATE). EDA Consortium / IEEE; 2016:912-917.
LibreCat: /record/168

Wiersema T, Wu S, Platzner M. On-The-Fly Verification of Reconfigurable Image Processing Modules based on a Proof-Carrying Hardware Approach. In: Proceedings of the International Symposium in Reconfigurable Computing (ARC). LNCS. ; 2015:365--372. doi:10.1007/978-3-319-16214-0_32
LibreCat: /record/269
DOI: 10.1007/978-3-319-16214-0_32

Knorr C. Evaluation von Bildverarbeitungsalgorithmen in heterogenen Rechenknoten. Universität Paderborn; 2015.
LibreCat: /record/3364

Torresen J, Plessl C, Yao X. Self-Aware and Self-Expressive Systems – Guest Editor’s Introduction. IEEE Computer. 2015;48(7):18-20. doi:10.1109/MC.2015.205
LibreCat: /record/1772
DOI: 10.1109/MC.2015.205

Ahmed AF. Self-Optimizing Organic Cache. Paderborn University; 2015.
LibreCat: /record/10615

Beisel T. Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing. Berlin: Logos Verlag Berlin GmbH; 2015.
LibreCat: /record/10624

Hangmann H. Evolution of Heat Flow Prediction Models for FPGA Devices. Paderborn University; 2015.
LibreCat: /record/10668

Haupt C. Computer Vision Basierte Klassifikation von HD EMG Signalen. Paderborn University; 2015.
LibreCat: /record/10671

Ho N, Ahmed AF, Kaufmann P, Platzner M. Microarchitectural optimization by means of reconfigurable and evolvable cache mappings. In: Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS). ; 2015:1-7. doi:10.1109/AHS.2015.7231178
LibreCat: /record/10673
DOI: 10.1109/AHS.2015.7231178

Kaufmann P, Shen C. Generator Start-up Sequences Optimization for Network Restoration Using Genetic Algorithm and Simulated Annealing. In: Genetic and Evolutionary Computation (GECCO). ACM; 2015:409-416.
LibreCat: /record/10693

Meisner S, Platzner M. Comparison of thread signatures for error detection in hybrid multi-cores. In: Field Programmable Technology (FPT), 2015 International Conference On. FPT. ; 2015:212-215. doi:10.1109/FPT.2015.7393153
LibreCat: /record/10711
DOI: 10.1109/FPT.2015.7393153

Meißner R. Konzept Und Implementation Einer Benutzeroberfläche Zur Generierung Virtueller FPGAs. Universität Paderborn; 2015.
LibreCat: /record/10714

Posewsky T. Acceleration of Artificial Neural Networks on a Zynq Platform. Paderborn University; 2015.
LibreCat: /record/10726

M. Mora A, Squillero G, Agapitos A, et al. Applications of Evolutionary Computation - 18th European Conference, EvoApplications. Vol 9028. Copenhagen, Denmark: Springer; 2015.
LibreCat: /record/10757

H.W. Leong P, Amano H, Anderson J, et al. Significant papers from the first 25 years of the FPL conference. In: Proceedings of the 25th International Conference on Field Programmable Logic and Applications (FPL). Imperial College; 2015:1-3. doi:10.1109/FPL.2015.7293747
LibreCat: /record/10765
DOI: 10.1109/FPL.2015.7293747

Ghribi I, Ben Abdallah R, Khalgui M, Platzner M. New Codesign Solutions for Modelling and Partitioning of Probabilistic Reconfigurable Embedded Software. In: Proceedings of the 29th European Simulation and Modelling Conference (ESM). ; 2015.
LibreCat: /record/10767

Ghasemzadeh Mohammadi H, Gaillardon P-E, De Micheli G. From Defect Analysis to Gate-Level Fault Modeling of Controllable-Polarity Silicon Nanowires. IEEE Transactions on Nanotechnology. 2015;14(6):1117-1126. doi:10.1109/TNANO.2015.2482359
LibreCat: /record/10770
DOI: 10.1109/TNANO.2015.2482359

Ghasemzadeh Mohammadi H, Gaillardon P-E, Zhang J, De Micheli G, Sanchez E, Reorda MS. On the design of a fault tolerant ripple-carry adder with controllable-polarity transistors. In: 2015 IEEE Computer Society Annual Symposium on VLSI. IEEE; 2015:491-496. doi:10.1109/ISVLSI.2015.13
LibreCat: /record/10771
DOI: 10.1109/ISVLSI.2015.13

Ghasemzadeh Mohammadi H, Gaillardon P-E, De Micheli G. Fault modeling in controllable polarity silicon nanowire circuits. In: Proceedings of the 2015 Design, Automation &; Test in Europe Conference \'26; Exhibition. EDA Consortium; 2015:453-458. doi:10.7873/DATE.2015.0428
LibreCat: /record/10772
DOI: 10.7873/DATE.2015.0428

Guettatfi Z, Kermia O, Khouas A. Over effective hard real-time hardware tasks scheduling and allocation. In: 25th International Conference on Field Programmable Logic and Applications (FPL). Imperial College; 2015. doi:10.1109/FPL.2015.7293994
LibreCat: /record/10779
DOI: 10.1109/FPL.2015.7293994

Graf T, Platzner M. Adaptive Playouts in Monte-Carlo Tree Search with Policy-Gradient Reinforcement Learning. In: Advances in Computer Games: 14th International Conference, ACG 2015, Leiden, The Netherlands, July 1-3, 2015, Revised Selected Papers. Springer International Publishing; 2015:1-11. doi:10.1007/978-3-319-27992-3_1
LibreCat: /record/13153
DOI: 10.1007/978-3-319-27992-3_1

Kenter T, Schmitz H, Plessl C. Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study. International Journal of Reconfigurable Computing (IJRC). 2015;2015. doi:10.1155/2015/859425
LibreCat: /record/296
DOI: 10.1155/2015/859425

Damschen M, Plessl C. Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores. In: Proceedings of the 5th International Workshop on Adaptive Self-Tuning Computing Systems (ADAPT). ; 2015.
LibreCat: /record/303
arXiv: 1412.3906

Schumacher J, T. Anderson J, Borga A, et al. Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm. In: Proc. Int. Conf. on Distributed Event-Based Systems (DEBS). ACM; 2015. doi:10.1145/2675743.2771824
LibreCat: /record/1773
DOI: 10.1145/2675743.2771824

Plessl C, Platzner M, Schreier PJ. Aktuelles Schlagwort: Approximate Computing. Informatik Spektrum. 2015;(5):396-399. doi:10.1007/s00287-015-0911-z
LibreCat: /record/1768
DOI: 10.1007/s00287-015-0911-z

Damschen M, Riebler H, Vaz GF, Plessl C. Transparent offloading of computational hotspots from binary code to Xeon Phi. In: Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE). EDA Consortium / IEEE; 2015:1078-1083. doi:10.7873/DATE.2015.1124
LibreCat: /record/238
DOI: 10.7873/DATE.2015.1124

Meisner S, Platzner M. Thread Shadowing: Using Dynamic Redundancy on Hybrid Multi-cores for Error Detection. In: Goehringer D, Santambrogio M, Cardoso JP, Bertels K, eds. Proceedings of the 10th International Symposium on Applied Reconfigurable Computing (ARC). Lecture Notes in Computer Science. Springer; 2014:283-290. doi:10.1007/978-3-319-05960-0_30
LibreCat: /record/347
DOI: 10.1007/978-3-319-05960-0_30

Graf T, Schaefers L, Platzner M. On Semeai Detection in Monte-Carlo Go. In: Proc. Conf. on Computers and Games (CG). Lecture Notes in Computer Science. Switzerland: Springer; 2014:14-25. doi:10.1007/978-3-319-09165-5_2
LibreCat: /record/1782
DOI: 10.1007/978-3-319-09165-5_2

Wiersema T, Drzevitzky S, Platzner M. Memory Security in Reconfigurable Computers: Combining Formal Verification with Monitoring. In: Proceedings of the International Conference on Field-Programmable Technology (FPT). ; 2014:167-174. doi:10.1109/FPT.2014.7082771
LibreCat: /record/399
DOI: 10.1109/FPT.2014.7082771

Jakobs M-C, Platzner M, Wiersema T, Wehrheim H. Integrating Software and Hardware Verification. In: Albert E, Sekerinski E, eds. Proceedings of the 11th International Conference on Integrated Formal Methods (IFM). LNCS. ; 2014:307-322. doi:10.1007/978-3-319-10181-1_19
LibreCat: /record/408
DOI: 10.1007/978-3-319-10181-1_19

Wiersema T, Bockhorn A, Platzner M. Embedding FPGA Overlays into Configurable Systems-on-Chip: ReconOS meets ZUMA. In: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig). ; 2014:1-6. doi:10.1109/ReConFig.2014.7032514
LibreCat: /record/433
DOI: 10.1109/ReConFig.2014.7032514

Schaefers L, Platzner M. A Novel Technique and its Application to Computer Go. IEEE Transactions on Computational Intelligence and AI in Games. 2014;6(3):361-374. doi:10.1109/TCIAIG.2014.2346997
LibreCat: /record/10602
DOI: 10.1109/TCIAIG.2014.2346997

Giefers H, Platzner M. An FPGA-based Reconfigurable Mesh Many-Core. IEEE Transactions on Computers. 2014;63(12):2919-2932. doi:10.1109/TC.2013.174
LibreCat: /record/10603
DOI: 10.1109/TC.2013.174

Anwer J, Platzner M, Meisner S. FPGA Redundancy Configurations: An Automated Design Space Exploration. In: Reconfigurable Architectures Workshop (RAW). RAW. ; 2014. doi:10.1109/IPDPSW.2014.37
LibreCat: /record/10621
DOI: 10.1109/IPDPSW.2014.37

Bockhorn A. Echtzeit Klassifikation von SEMG Signalen Mit Einem Low-Cost DSP Evaluation Board. Paderborn University; 2014.
LibreCat: /record/10627

Boschmann A, Platzner M. A computer vision-based approach to high density EMG pattern recognition using structural similarity. In: Proc. MyoElectric Controls Symposium (MEC). ; 2014.
LibreCat: /record/10632

Boschmann A, Platzner M. Towards robust HD EMG pattern recognition: Reducing electrode displacement effect using structural similarity. In: Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC). ; 2014.
LibreCat: /record/10633

Brand M. A Generalized Loop Accelerator Implemented as a Coarse-Grained Array. Paderborn University; 2014.
LibreCat: /record/10640

Damschen M. Easy-to-Use-on-the-Fly Binary Program Acceleration on Many-Cores. Paderborn University; 2014.
LibreCat: /record/10645

Glette K, Kaufmann P. Lookup Table Partial Reconfiguration for an Evolvable Hardware Classifier System. In: IEEE Congress on Evolutionary Computation (CEC). ; 2014.
LibreCat: /record/10654

Hagedorn C. Entwicklung Einer Codegrößenoptimierten Softwarebibliothek Für 8-Bit Mikrocontroller in Netzunabhängigen Notleuchten. Paderborn University; 2014.
LibreCat: /record/10665

Ho N, Kaufmann P, Platzner M. A hardware/software infrastructure for performance monitoring on LEON3 multicore platforms. In: 24th Intl. Conf. on Field Programmable Logic and Applications (FPL). ; 2014:1-4. doi:10.1109/FPL.2014.6927437
LibreCat: /record/10674
DOI: 10.1109/FPL.2014.6927437

Ho N, Kaufmann P, Platzner M. Towards self-adaptive caches: A run-time reconfigurable multi-core infrastructure. In: 2014 IEEE Intl. Conf. on Evolvable Systems (ICES). ; 2014:31-37. doi:10.1109/ICES.2014.7008719
LibreCat: /record/10677
DOI: 10.1109/ICES.2014.7008719

König F. EMG-Basierte Simultane Und Proportionale Online-Steuerung Einer Virtuellen Prothese. Paderborn University; 2014.
LibreCat: /record/10679

Koch B. Hardware Acceleration of Mechatronic Controllers on a Zynq Platform FPGA. Paderborn University; 2014.
LibreCat: /record/10701

Mittendorf R. Advanced AES-Key Recovery from Decayed RAM Using Multi-Threading and FPGAs. Paderborn University; 2014.
LibreCat: /record/10715

Rüthing C. The Xilinx Zynq Architecture as a Platform for Reconfigurable Heterogeneous Multi-Cores. Paderborn University; 2014.
LibreCat: /record/10732

Schäfers L. Parallel Monte-Carlo Tree Search for HPC Systems and Its Application to Computer Go. Berlin: Logos Verlag Berlin GmbH; 2014.
LibreCat: /record/10733

Shen C, Kaufmann P, Braun M. Optimizing the Generator Start-up Sequence After a Power System Blackout. In: IEEE Power and Energy Society General Meeting (IEEE GM). ; 2014.
LibreCat: /record/10738

Shen C, Kaufmann P, Braun M. A New Distribution Network Reconfiguration and Restoration Path Selection Algorithm. In: Power Systems Computation Conference (PSCC). IEEE; 2014.
LibreCat: /record/10739

Surmund S. Multithreaded Parallelization of Mechatronic Controllers on a Zynq Platform FPGA. Paderborn University; 2014.
LibreCat: /record/10744

I. Esparcia-Alc\rquote azar A, Eiben AE, Agapitos A, et al. Applications of Evolutionary Computation - 17th European Conference, EvoApplications. Vol 8602. Granada, Spain: Springer; 2014.
LibreCat: /record/10756

Anwer J, Platzner M. Analytic reliability evaluation for fault-tolerant circuit structures on FPGAs. In: IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT). IEEE; 2014:177-184. doi:10.1109/DFT.2014.6962108
LibreCat: /record/10764
DOI: 10.1109/DFT.2014.6962108

Ghasemzadeh Mohammadi H, Gaillardon P-E, Yazdani M, De Micheli G. Fast process variation analysis in nano-scaled technologies using column-wise sparse parameter selection. In: 2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH). IEEE; 2014:163-168. doi:10.1109/NANOARCH.2014.6880479
LibreCat: /record/10773
DOI: 10.1109/NANOARCH.2014.6880479

Graf T, Platzner M. Common Fate Graph Patterns in Monte Carlo Tree Search for Computer Go. In: 2014 IEEE Conference on Computational Intelligence and Games. ; 2014:1-8. doi:10.1109/CIG.2014.6932863
LibreCat: /record/13154
DOI: 10.1109/CIG.2014.6932863

Platzner M, Plessl C. Verschiebungen an der Grenze zwischen Hardware und Software. In: Künsemöller J, Eke NO, Foit L, Kaerlein T, eds. Logiken strukturbildender Prozesse: Automatismen. Schriftenreihe des Graduiertenkollegs “Automatismen.” Wilhelm Fink; 2014:123-144.
LibreCat: /record/335

Kenter T, Vaz GF, Plessl C. Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer. In: Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC). Vol 8405. Lecture Notes in Computer Science (LNCS). Springer International Publishing; 2014:144-155. doi:10.1007/978-3-319-05960-0_13
LibreCat: /record/388
DOI: 10.1007/978-3-319-05960-0_13

Agne A, Hangmann H, Happe M, Platzner M, Plessl C. Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators. Microprocessors and Microsystems. 2014;38(8, Part B):911-919. doi:10.1016/j.micpro.2013.12.001
LibreCat: /record/363
DOI: 10.1016/j.micpro.2013.12.001

Riebler H, Kenter T, Plessl C, Sorge C. Reconstructing AES Key Schedules from Decayed Memory with FPGAs. In: Proceedings of Field-Programmable Custom Computing Machines (FCCM). IEEE; 2014:222-229. doi:10.1109/FCCM.2014.67
LibreCat: /record/377
DOI: 10.1109/FCCM.2014.67