Hermansen, Sven. Custom Memory Controller for ReconOS. Paderborn University, 2016.
LibreCat: /record/10781

Lewis, Peter R., et al., editors. Self-Aware Computing Systems: An Engineering Approach. Springer, 2016, doi:10.1007/978-3-319-39675-0.
LibreCat: /record/12972
DOI: 10.1007/978-3-319-39675-0

Boschmann, Alexander, et al. “FPGA-Based Acceleration of High Density Myoelectric Signal Processing.”10.1109/reconfig.2015.7393312__2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2016, doi:10.1109/reconfig.2015.7393312.
LibreCat: /record/15873
DOI: 10.1109/reconfig.2015.7393312

Graf, Tobias, and Marco Platzner. “Using Deep Convolutional Neural Networks in Monte Carlo Tree Search.” Computer and Games, 2016.
LibreCat: /record/13151

Graf, Tobias, and Marco Platzner. “Monte-Carlo Simulation Balancing Revisited.” IEEE Computational Intelligence and Games, 2016.
LibreCat: /record/13152

Wiersema, Tobias, and Marco Platzner. “Verifying Worst-Case Completion Times for Reconfigurable Hardware Modules Using Proof-Carrying Hardware.”10.1109/ReCoSoC.2016.7533910__Proceedings of the 11th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC 2016), 2016, pp. 1--8, doi:10.1109/ReCoSoC.2016.7533910.
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DOI: 10.1109/ReCoSoC.2016.7533910

Agne, Andreas, et al. “ReconOS.”10.1007/978-3-319-26408-0_13__FPGAs for Software Programmers, edited by Dirk Koch et al., Springer International Publishing, 2016, pp. 227–44, doi:10.1007/978-3-319-26408-0_13.
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DOI: 10.1007/978-3-319-26408-0_13

Agne, Andreas, et al. “Self-Aware Compute Nodes.”10.1007/978-3-319-39675-0_8__Self-Aware Computing Systems, Springer International Publishing, 2016, pp. 145–65, doi:10.1007/978-3-319-39675-0_8.
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DOI: 10.1007/978-3-319-39675-0_8

Lösch, Achim, et al. “Performance-Centric Scheduling with Task Migration for a Heterogeneous Compute Node in the Data Center.” Proceedings of the 2016 Design, Automation &; Test in Europe Conference &; Exhibition (DATE), EDA Consortium / IEEE, 2016, pp. 912–17.
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Wiersema, Tobias, et al. “On-The-Fly Verification of Reconfigurable Image Processing Modules Based on a Proof-Carrying Hardware Approach.”10.1007/978-3-319-16214-0_32__Proceedings of the International Symposium in Reconfigurable Computing (ARC), 2015, pp. 365--372, doi:10.1007/978-3-319-16214-0_32.
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DOI: 10.1007/978-3-319-16214-0_32

Knorr, Christoph. Evaluation von Bildverarbeitungsalgorithmen in heterogenen Rechenknoten. Universität Paderborn, 2015.
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Torresen, Jim, et al. “Self-Aware and Self-Expressive Systems – Guest Editor’s Introduction.”10.1109/MC.2015.205__IEEE Computer, vol. 48, no. 7, IEEE Computer Society, 2015, pp. 18–20, doi:10.1109/MC.2015.205.
LibreCat: /record/1772
DOI: 10.1109/MC.2015.205

Ahmed, Abdullah Fathi. Self-Optimizing Organic Cache. Paderborn University, 2015.
LibreCat: /record/10615

Beisel, Tobias. Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing. Logos Verlag Berlin GmbH, 2015.
LibreCat: /record/10624

Hangmann, Hendrik. Evolution of Heat Flow Prediction Models for FPGA Devices. Paderborn University, 2015.
LibreCat: /record/10668

Haupt, Christian. Computer Vision Basierte Klassifikation von HD EMG Signalen. Paderborn University, 2015.
LibreCat: /record/10671

Ho, Nam, et al. “Microarchitectural Optimization by Means of Reconfigurable and Evolvable Cache Mappings.”10.1109/AHS.2015.7231178__Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS), 2015, pp. 1–7, doi:10.1109/AHS.2015.7231178.
LibreCat: /record/10673
DOI: 10.1109/AHS.2015.7231178

Kaufmann, Paul, and Cong Shen. “Generator Start-up Sequences Optimization for Network Restoration Using Genetic Algorithm and Simulated Annealing.” Genetic and Evolutionary Computation (GECCO), ACM, 2015, pp. 409–16.
LibreCat: /record/10693

Meisner, Sebastian, and Marco Platzner. “Comparison of Thread Signatures for Error Detection in Hybrid Multi-Cores.”10.1109/FPT.2015.7393153__Field Programmable Technology (FPT), 2015 International Conference On, 2015, pp. 212–15, doi:10.1109/FPT.2015.7393153.
LibreCat: /record/10711
DOI: 10.1109/FPT.2015.7393153

Meißner, Roland. Konzept Und Implementation Einer Benutzeroberfläche Zur Generierung Virtueller FPGAs. Universität Paderborn, 2015.
LibreCat: /record/10714

Posewsky, Thorbjörn. Acceleration of Artificial Neural Networks on a Zynq Platform. Paderborn University, 2015.
LibreCat: /record/10726

M. Mora, Antonio, et al. Applications of Evolutionary Computation - 18th European Conference, EvoApplications. Vol. 9028, Springer, 2015.
LibreCat: /record/10757

H.W. Leong, Philip, et al. “Significant Papers from the First 25 Years of the FPL Conference.”10.1109/FPL.2015.7293747__Proceedings of the 25th International Conference on Field Programmable Logic and Applications (FPL), Imperial College, 2015, pp. 1–3, doi:10.1109/FPL.2015.7293747.
LibreCat: /record/10765
DOI: 10.1109/FPL.2015.7293747

Ghribi, Ines, et al. “New Codesign Solutions for Modelling and Partitioning of Probabilistic Reconfigurable Embedded Software.” Proceedings of the 29th European Simulation and Modelling Conference (ESM), 2015.
LibreCat: /record/10767

Ghasemzadeh Mohammadi, Hassan, et al. “From Defect Analysis to Gate-Level Fault Modeling of Controllable-Polarity Silicon Nanowires.”10.1109/TNANO.2015.2482359__IEEE Transactions on Nanotechnology, vol. 14, no. 6, IEEE, 2015, pp. 1117–26, doi:10.1109/TNANO.2015.2482359.
LibreCat: /record/10770
DOI: 10.1109/TNANO.2015.2482359

Ghasemzadeh Mohammadi, Hassan, et al. “On the Design of a Fault Tolerant Ripple-Carry Adder with Controllable-Polarity Transistors.”10.1109/ISVLSI.2015.13__2015 IEEE Computer Society Annual Symposium on VLSI, IEEE, 2015, pp. 491–96, doi:10.1109/ISVLSI.2015.13.
LibreCat: /record/10771
DOI: 10.1109/ISVLSI.2015.13

Ghasemzadeh Mohammadi, Hassan, et al. “Fault Modeling in Controllable Polarity Silicon Nanowire Circuits.”10.7873/DATE.2015.0428__Proceedings of the 2015 Design, Automation &; Test in Europe Conference \'26; Exhibition, EDA Consortium, 2015, pp. 453–58, doi:10.7873/DATE.2015.0428.
LibreCat: /record/10772
DOI: 10.7873/DATE.2015.0428

Guettatfi, Zakarya, et al. “Over Effective Hard Real-Time Hardware Tasks Scheduling and Allocation.”10.1109/FPL.2015.7293994__25th International Conference on Field Programmable Logic and Applications (FPL), Imperial College, 2015, doi:10.1109/FPL.2015.7293994.
LibreCat: /record/10779
DOI: 10.1109/FPL.2015.7293994

Graf, Tobias, and Marco Platzner. “Adaptive Playouts in Monte-Carlo Tree Search with Policy-Gradient Reinforcement Learning.”10.1007/978-3-319-27992-3_1__Advances in Computer Games: 14th International Conference, ACG 2015, Leiden, The Netherlands, July 1-3, 2015, Revised Selected Papers, Springer International Publishing, 2015, pp. 1–11, doi:10.1007/978-3-319-27992-3_1.
LibreCat: /record/13153
DOI: 10.1007/978-3-319-27992-3_1

Kenter, Tobias, et al. “Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study.”10.1155/2015/859425__International Journal of Reconfigurable Computing (IJRC), vol. 2015, 859425, Hindawi, 2015, doi:10.1155/2015/859425.
LibreCat: /record/296
DOI: 10.1155/2015/859425

Damschen, Marvin, and Christian Plessl. “Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores.” Proceedings of the 5th International Workshop on Adaptive Self-Tuning Computing Systems (ADAPT), 2015.
LibreCat: /record/303
arXiv: 1412.3906

Schumacher, Jörn, et al. “Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm.”10.1145/2675743.2771824__Proc. Int. Conf. on Distributed Event-Based Systems (DEBS), ACM, 2015, doi:10.1145/2675743.2771824.
LibreCat: /record/1773
DOI: 10.1145/2675743.2771824

Plessl, Christian, et al. “Aktuelles Schlagwort: Approximate Computing.”10.1007/s00287-015-0911-z__Informatik Spektrum, no. 5, Springer, 2015, pp. 396–99, doi:10.1007/s00287-015-0911-z.
LibreCat: /record/1768
DOI: 10.1007/s00287-015-0911-z

Damschen, Marvin, et al. “Transparent Offloading of Computational Hotspots from Binary Code to Xeon Phi.”10.7873/DATE.2015.1124__Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE), EDA Consortium / IEEE, 2015, pp. 1078–83, doi:10.7873/DATE.2015.1124.
LibreCat: /record/238
DOI: 10.7873/DATE.2015.1124

Meisner, Sebastian, and Marco Platzner. “Thread Shadowing: Using Dynamic Redundancy on Hybrid Multi-Cores for Error Detection.”10.1007/978-3-319-05960-0_30__Proceedings of the 10th International Symposium on Applied Reconfigurable Computing (ARC), edited by Diana Goehringer et al., Springer, 2014, pp. 283–90, doi:10.1007/978-3-319-05960-0_30.
LibreCat: /record/347
DOI: 10.1007/978-3-319-05960-0_30

Graf, Tobias, et al. “On Semeai Detection in Monte-Carlo Go.”10.1007/978-3-319-09165-5_2__Proc. Conf. on Computers and Games (CG), no. 8427, Springer, 2014, pp. 14–25, doi:10.1007/978-3-319-09165-5_2.
LibreCat: /record/1782
DOI: 10.1007/978-3-319-09165-5_2

Wiersema, Tobias, et al. “Memory Security in Reconfigurable Computers: Combining Formal Verification with Monitoring.”10.1109/FPT.2014.7082771__Proceedings of the International Conference on Field-Programmable Technology (FPT), 2014, pp. 167–74, doi:10.1109/FPT.2014.7082771.
LibreCat: /record/399
DOI: 10.1109/FPT.2014.7082771

Jakobs, Marie-Christine, et al. “Integrating Software and Hardware Verification.”10.1007/978-3-319-10181-1_19__Proceedings of the 11th International Conference on Integrated Formal Methods (IFM), edited by Elvira Albert and Emil Sekerinski, 2014, pp. 307–22, doi:10.1007/978-3-319-10181-1_19.
LibreCat: /record/408
DOI: 10.1007/978-3-319-10181-1_19

Wiersema, Tobias, et al. “Embedding FPGA Overlays into Configurable Systems-on-Chip: ReconOS Meets ZUMA.”10.1109/ReConFig.2014.7032514__Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 2014, pp. 1–6, doi:10.1109/ReConFig.2014.7032514.
LibreCat: /record/433
DOI: 10.1109/ReConFig.2014.7032514

Schaefers, Lars, and Marco Platzner. “A Novel Technique and Its Application to Computer Go.”10.1109/TCIAIG.2014.2346997__IEEE Transactions on Computational Intelligence and AI in Games, vol. 6, no. 3, 2014, pp. 361–74, doi:10.1109/TCIAIG.2014.2346997.
LibreCat: /record/10602
DOI: 10.1109/TCIAIG.2014.2346997

Giefers, Heiner, and Marco Platzner. “An FPGA-Based Reconfigurable Mesh Many-Core.”10.1109/TC.2013.174__IEEE Transactions on Computers, vol. 63, no. 12, 2014, pp. 2919–32, doi:10.1109/TC.2013.174.
LibreCat: /record/10603
DOI: 10.1109/TC.2013.174

Anwer, Jahanzeb, et al. “FPGA Redundancy Configurations: An Automated Design Space Exploration.”10.1109/IPDPSW.2014.37__Reconfigurable Architectures Workshop (RAW), 2014, doi:10.1109/IPDPSW.2014.37.
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DOI: 10.1109/IPDPSW.2014.37

Bockhorn, Arne. Echtzeit Klassifikation von SEMG Signalen Mit Einem Low-Cost DSP Evaluation Board. Paderborn University, 2014.
LibreCat: /record/10627

Boschmann, Alexander, and Marco Platzner. “A Computer Vision-Based Approach to High Density EMG Pattern Recognition Using Structural Similarity.” Proc. MyoElectric Controls Symposium (MEC), 2014.
LibreCat: /record/10632

Boschmann, Alexander, and Marco Platzner. “Towards Robust HD EMG Pattern Recognition: Reducing Electrode Displacement Effect Using Structural Similarity.” Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC), 2014.
LibreCat: /record/10633

Brand, Marcel. A Generalized Loop Accelerator Implemented as a Coarse-Grained Array. Paderborn University, 2014.
LibreCat: /record/10640

Damschen, Marvin. Easy-to-Use-on-the-Fly Binary Program Acceleration on Many-Cores. Paderborn University, 2014.
LibreCat: /record/10645

Glette, Kyrre, and Paul Kaufmann. “Lookup Table Partial Reconfiguration for an Evolvable Hardware Classifier System.” IEEE Congress on Evolutionary Computation (CEC), 2014.
LibreCat: /record/10654

Hagedorn, Christoph. Entwicklung Einer Codegrößenoptimierten Softwarebibliothek Für 8-Bit Mikrocontroller in Netzunabhängigen Notleuchten. Paderborn University, 2014.
LibreCat: /record/10665

Ho, Nam, et al. “A Hardware/Software Infrastructure for Performance Monitoring on LEON3 Multicore Platforms.”10.1109/FPL.2014.6927437__24th Intl. Conf. on Field Programmable Logic and Applications (FPL), 2014, pp. 1–4, doi:10.1109/FPL.2014.6927437.
LibreCat: /record/10674
DOI: 10.1109/FPL.2014.6927437

Ho, Nam, et al. “Towards Self-Adaptive Caches: A Run-Time Reconfigurable Multi-Core Infrastructure.”10.1109/ICES.2014.7008719__2014 IEEE Intl. Conf. on Evolvable Systems (ICES), 2014, pp. 31–37, doi:10.1109/ICES.2014.7008719.
LibreCat: /record/10677
DOI: 10.1109/ICES.2014.7008719

König, Fabian. EMG-Basierte Simultane Und Proportionale Online-Steuerung Einer Virtuellen Prothese. Paderborn University, 2014.
LibreCat: /record/10679

Koch, Benjamin. Hardware Acceleration of Mechatronic Controllers on a Zynq Platform FPGA. Paderborn University, 2014.
LibreCat: /record/10701

Mittendorf, Robert. Advanced AES-Key Recovery from Decayed RAM Using Multi-Threading and FPGAs. Paderborn University, 2014.
LibreCat: /record/10715

Rüthing, Christoph. The Xilinx Zynq Architecture as a Platform for Reconfigurable Heterogeneous Multi-Cores. Paderborn University, 2014.
LibreCat: /record/10732

Schäfers, Lars. Parallel Monte-Carlo Tree Search for HPC Systems and Its Application to Computer Go. Logos Verlag Berlin GmbH, 2014.
LibreCat: /record/10733

Shen, Cong, et al. “Optimizing the Generator Start-up Sequence After a Power System Blackout.” IEEE Power and Energy Society General Meeting (IEEE GM), 2014.
LibreCat: /record/10738

Shen, Cong, et al. “A New Distribution Network Reconfiguration and Restoration Path Selection Algorithm.” Power Systems Computation Conference (PSCC), IEEE, 2014.
LibreCat: /record/10739

Surmund, Sebastian. Multithreaded Parallelization of Mechatronic Controllers on a Zynq Platform FPGA. Paderborn University, 2014.
LibreCat: /record/10744

I. Esparcia-Alc\rquote azar, Anna, et al. Applications of Evolutionary Computation - 17th European Conference, EvoApplications. Vol. 8602, Springer, 2014.
LibreCat: /record/10756

Anwer, Jahanzeb, and Marco Platzner. “Analytic Reliability Evaluation for Fault-Tolerant Circuit Structures on FPGAs.”10.1109/DFT.2014.6962108__IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), IEEE, 2014, pp. 177–84, doi:10.1109/DFT.2014.6962108.
LibreCat: /record/10764
DOI: 10.1109/DFT.2014.6962108

Ghasemzadeh Mohammadi, Hassan, et al. “Fast Process Variation Analysis in Nano-Scaled Technologies Using Column-Wise Sparse Parameter Selection.”10.1109/NANOARCH.2014.6880479__2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), IEEE, 2014, pp. 163–68, doi:10.1109/NANOARCH.2014.6880479.
LibreCat: /record/10773
DOI: 10.1109/NANOARCH.2014.6880479

Graf, Tobias, and Marco Platzner. “Common Fate Graph Patterns in Monte Carlo Tree Search for Computer Go.”10.1109/CIG.2014.6932863__2014 IEEE Conference on Computational Intelligence and Games, 2014, pp. 1–8, doi:10.1109/CIG.2014.6932863.
LibreCat: /record/13154
DOI: 10.1109/CIG.2014.6932863

Platzner, Marco, and Christian Plessl. “Verschiebungen an der Grenze zwischen Hardware und Software.” Logiken strukturbildender Prozesse: Automatismen, edited by Jörn Künsemöller et al., Wilhelm Fink, 2014, pp. 123–44.
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Kenter, Tobias, et al. “Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer.”10.1007/978-3-319-05960-0_13__Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC), vol. 8405, Springer International Publishing, 2014, pp. 144–55, doi:10.1007/978-3-319-05960-0_13.
LibreCat: /record/388
DOI: 10.1007/978-3-319-05960-0_13

Agne, Andreas, et al. “Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators.”10.1016/j.micpro.2013.12.001__Microprocessors and Microsystems, vol. 38, no. 8, Part B, Elsevier, 2014, pp. 911–19, doi:10.1016/j.micpro.2013.12.001.
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DOI: 10.1016/j.micpro.2013.12.001

Riebler, Heinrich, et al. “Reconstructing AES Key Schedules from Decayed Memory with FPGAs.”10.1109/FCCM.2014.67__Proceedings of Field-Programmable Custom Computing Machines (FCCM), IEEE, 2014, pp. 222–29, doi:10.1109/FCCM.2014.67.
LibreCat: /record/377
DOI: 10.1109/FCCM.2014.67

Agne, Andreas, et al. “Self-Awareness as a Model for Designing and Operating Heterogeneous Multicores.”10.1145/2617596__ACM Transactions on Reconfigurable Technology and Systems (TRETS), vol. 7, no. 2, 13, ACM, 2014, doi:10.1145/2617596.
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DOI: 10.1145/2617596

Agne, Andreas, et al. “ReconOS - An Operating System Approach for Reconfigurable Computing.”10.1109/MM.2013.110__IEEE Micro, vol. 34, no. 1, IEEE, 2014, pp. 60–71, doi:10.1109/MM.2013.110.
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DOI: 10.1109/MM.2013.110

C. Durelli, Gianluca, et al. “Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach.”10.1109/ISPA.2014.27__Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA), IEEE, 2014, pp. 142–49, doi:10.1109/ISPA.2014.27.
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DOI: 10.1109/ISPA.2014.27

Vaz, Gavin Francis, et al. “Deferring Accelerator Offloading Decisions to Application Runtime.”10.1109/ReConFig.2014.7032509__Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2014, pp. 1–8, doi:10.1109/ReConFig.2014.7032509.
LibreCat: /record/439
DOI: 10.1109/ReConFig.2014.7032509

Kenter, Tobias, et al. “Kernel-Centric Acceleration of High Accuracy Stereo-Matching.”10.1109/ReConFig.2014.7032535__Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2014, pp. 1–8, doi:10.1109/ReConFig.2014.7032535.
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DOI: 10.1109/ReConFig.2014.7032535

C. Durelli, Gianluca, et al. “SAVE: Towards Efficient Resource Management in Heterogeneous System Architectures.”10.1007/978-3-319-05960-0_38__Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC), Springer, 2014, doi:10.1007/978-3-319-05960-0_38.
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DOI: 10.1007/978-3-319-05960-0_38

Giefers, Heiner, et al. “Accelerating Finite Difference Time Domain Simulations with Reconfigurable Dataflow Computers.”10.1145/2641361.2641372__ACM SIGARCH Computer Architecture News, vol. 41, no. 5, ACM, 2014, pp. 65–70, doi:10.1145/2641361.2641372.
LibreCat: /record/1779
DOI: 10.1145/2641361.2641372

Kaufmann, Paul. Adapting Hardware Systems by Means of Multi-Objective Evolution. Logos Verlag Berlin GmbH, 2013.
LibreCat: /record/11619

Kasap, Server, and Soydan Redif. “FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm.”10.1109/SIU.2013.6531530__Proc. IEEE Signal Processing and Communications Conf. (SUI), IEEE, 2013, doi:10.1109/SIU.2013.6531530.
LibreCat: /record/1786
DOI: 10.1109/SIU.2013.6531530

Kasap, Server, and Soydan Redif. “Novel Field-Programmable Gate Array Architecture for Computing the Eigenvalue Decomposition of Para-Hermitian Polynomial Matrices.”10.1109/TVLSI.2013.2248069__IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 22, no. 3, IEEE, 2013, pp. 522–36, doi:10.1109/TVLSI.2013.2248069.
LibreCat: /record/1792
DOI: 10.1109/TVLSI.2013.2248069

Happe, Markus. Performance and Thermal Management on Self-Adaptive Hybrid Multi-Cores. Logos Verlag Berlin GmbH, 2013.
LibreCat: /record/501

Happe, Markus, et al. “A Self-Adaptive Heterogeneous Multi-Core Architecture for Embedded Real-Time Video Object Tracking.”doi:10.1007/s11554-011-0212-y__International Journal of Real-Time Image Processing, vol. 8, no. 1, Springer, 2013, pp. 95–110, doi:doi:10.1007/s11554-011-0212-y.
LibreCat: /record/10604
DOI: doi:10.1007/s11554-011-0212-y

Anwer, Jahanzeb, et al. “Dynamic Reliability Management: Reconfiguring Reliability-Levels of Hardware Designs at Runtime.”10.1109/ReConFig.2013.6732280__Reconfigurable Computing and FPGAs (ReConFig), 2013 International Conference On, 2013, pp. 1–6, doi:10.1109/ReConFig.2013.6732280.
LibreCat: /record/10620
DOI: 10.1109/ReConFig.2013.6732280

Bick, Christian. Beschleunigung von Tiefenberechnung Aus Stereobildern Durch FPGA-Basierte Datenflussrechner. Paderborn University, 2013.
LibreCat: /record/10626

Boschmann, Alexander, et al. “Improving Transient State Myoelectric Signal Recognition in Hand Movement Classification Using Gyroscopes.” Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC), 2013.
LibreCat: /record/10634

Boschmann, Alexander, and Marco Platzner. “Reducing the Limb Position Effect in Pattern Recognition Based Myoelectric Control Using a High Density Electrode Array.” Proc. IEEE ISSNIP Biosignals and Biorobotics Conference (BRC), 2013.
LibreCat: /record/10635

Glette, Kyrre, et al. “Investigating Evolvable Hardware Classification for the BioSleeve Electromyographic Interface.” IEEE Intl. Conf. on Evolvable Systems (ICES), vol. 1, Springer, 2013, pp. 1–1.
LibreCat: /record/10655

Kaufmann, Paul. Adapting Hardware Systems by Means of Multi-Objective Evolution. Logos Verlag, 2013.
LibreCat: /record/10681

Kaufmann, Paul, et al. “Classification of Electromyographic Signals: Comparing Evolvable Hardware to Conventional Classifiers.”10.1109/TEVC.2012.2185845__IEEE Transactions on Evolutionary Computation, vol. 17, no. 1, 2013, pp. 46–63, doi:10.1109/TEVC.2012.2185845.
LibreCat: /record/10684
DOI: 10.1109/TEVC.2012.2185845

Knoop, Michael. Behavior Models for Electric Vehicles. IWES Kassel, 2013.
LibreCat: /record/10700

Nofen, Barbara. Verbesserung Der Erkennungsrate Eines Systems Zur Klassifikation von EMG-Signalen Durch Den Einsatz Eines Hybriden Lagesensors. Paderborn University, 2013.
LibreCat: /record/10720

Pudelko, Daniel. Überquerung Der Styx - Betriebsparametervariation Und Fehlerverhalten Eines Platform FPGAs. Paderborn University, 2013.
LibreCat: /record/10727

Riebler, Heinrich. Identifikation Und Wiederherstellung von Kryptographischen Schlüsseln Mit FPGAs. Paderborn University, 2013.
LibreCat: /record/10730

Sprenger, Alexander. MiBenchHybridf: Erweiterung Eines Benchmarks Um Hardwarebeschleunigung. Paderborn University, 2013.
LibreCat: /record/10741

Steppeler, Philipp. Beschleunigung von Einzelbild-Erkennungsverfahren Auf Datenfluss Basierenden HPC Systemen. Paderborn University, 2013.
LibreCat: /record/10743

Toebermann, Christian, et al. “Real-Time Simulation of Distribution Grids with High Penetration of Regenerative and Distributed Generation.” Real-Time Conference, OPAL RT Paris, 2013.
LibreCat: /record/10745

Ghasemzadeh Mohammadi, Hassan, et al. “A Fast TCAD-Based Methodology for Variation Analysis of Emerging Nano-Devices.”10.1109/DFT.2013.6653587__2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS), IEEE, 2013, pp. 83–88, doi:10.1109/DFT.2013.6653587.
LibreCat: /record/10774
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Gaillardon, Pierre-Emmanuel, et al. “Vertically-Stacked Silicon Nanowire Transistors with Controllable Polarity: A Robustness Study.”10.1109/LATW.2013.6562673__2013 14th Latin American Test Workshop-LATW, IEEE, 2013, pp. 1–6, doi:10.1109/LATW.2013.6562673.
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