Kaufmann P, Shen C. Generator Start-up Sequences Optimization for Network Restoration Using Genetic Algorithm and Simulated Annealing. In: Genetic and Evolutionary Computation (GECCO). ACM; 2015:409-416.
LibreCat: /record/10693

Meisner S, Platzner M. Comparison of thread signatures for error detection in hybrid multi-cores. In: Field Programmable Technology (FPT), 2015 International Conference On. FPT. ; 2015:212-215. doi:10.1109/FPT.2015.7393153
LibreCat: /record/10711
DOI: 10.1109/FPT.2015.7393153

Meißner R. Konzept Und Implementation Einer Benutzeroberfläche Zur Generierung Virtueller FPGAs. Universität Paderborn; 2015.
LibreCat: /record/10714

Posewsky T. Acceleration of Artificial Neural Networks on a Zynq Platform. Paderborn University; 2015.
LibreCat: /record/10726

M. Mora A, Squillero G, Agapitos A, et al. Applications of Evolutionary Computation - 18th European Conference, EvoApplications. Vol 9028. Copenhagen, Denmark: Springer; 2015.
LibreCat: /record/10757

H.W. Leong P, Amano H, Anderson J, et al. Significant papers from the first 25 years of the FPL conference. In: Proceedings of the 25th International Conference on Field Programmable Logic and Applications (FPL). Imperial College; 2015:1-3. doi:10.1109/FPL.2015.7293747
LibreCat: /record/10765
DOI: 10.1109/FPL.2015.7293747

Ghribi I, Ben Abdallah R, Khalgui M, Platzner M. New Codesign Solutions for Modelling and Partitioning of Probabilistic Reconfigurable Embedded Software. In: Proceedings of the 29th European Simulation and Modelling Conference (ESM). ; 2015.
LibreCat: /record/10767

Ghasemzadeh Mohammadi H, Gaillardon P-E, De Micheli G. From Defect Analysis to Gate-Level Fault Modeling of Controllable-Polarity Silicon Nanowires. IEEE Transactions on Nanotechnology. 2015;14(6):1117-1126. doi:10.1109/TNANO.2015.2482359
LibreCat: /record/10770
DOI: 10.1109/TNANO.2015.2482359

Ghasemzadeh Mohammadi H, Gaillardon P-E, Zhang J, De Micheli G, Sanchez E, Reorda MS. On the design of a fault tolerant ripple-carry adder with controllable-polarity transistors. In: 2015 IEEE Computer Society Annual Symposium on VLSI. IEEE; 2015:491-496. doi:10.1109/ISVLSI.2015.13
LibreCat: /record/10771
DOI: 10.1109/ISVLSI.2015.13

Ghasemzadeh Mohammadi H, Gaillardon P-E, De Micheli G. Fault modeling in controllable polarity silicon nanowire circuits. In: Proceedings of the 2015 Design, Automation &; Test in Europe Conference \'26; Exhibition. EDA Consortium; 2015:453-458. doi:10.7873/DATE.2015.0428
LibreCat: /record/10772
DOI: 10.7873/DATE.2015.0428

Guettatfi Z, Kermia O, Khouas A. Over effective hard real-time hardware tasks scheduling and allocation. In: 25th International Conference on Field Programmable Logic and Applications (FPL). Imperial College; 2015. doi:10.1109/FPL.2015.7293994
LibreCat: /record/10779
DOI: 10.1109/FPL.2015.7293994

Graf T, Platzner M. Adaptive Playouts in Monte-Carlo Tree Search with Policy-Gradient Reinforcement Learning. In: Advances in Computer Games: 14th International Conference, ACG 2015, Leiden, The Netherlands, July 1-3, 2015, Revised Selected Papers. Springer International Publishing; 2015:1-11. doi:10.1007/978-3-319-27992-3_1
LibreCat: /record/13153
DOI: 10.1007/978-3-319-27992-3_1

Kenter T, Schmitz H, Plessl C. Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study. International Journal of Reconfigurable Computing (IJRC). 2015;2015. doi:10.1155/2015/859425
LibreCat: /record/296
DOI: 10.1155/2015/859425

Damschen M, Plessl C. Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores. In: Proceedings of the 5th International Workshop on Adaptive Self-Tuning Computing Systems (ADAPT). ; 2015.
LibreCat: /record/303
arXiv: 1412.3906

Schumacher J, T. Anderson J, Borga A, et al. Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm. In: Proc. Int. Conf. on Distributed Event-Based Systems (DEBS). ACM; 2015. doi:10.1145/2675743.2771824
LibreCat: /record/1773
DOI: 10.1145/2675743.2771824

Plessl C, Platzner M, Schreier PJ. Aktuelles Schlagwort: Approximate Computing. Informatik Spektrum. 2015;(5):396-399. doi:10.1007/s00287-015-0911-z
LibreCat: /record/1768
DOI: 10.1007/s00287-015-0911-z

Damschen M, Riebler H, Vaz GF, Plessl C. Transparent offloading of computational hotspots from binary code to Xeon Phi. In: Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE). EDA Consortium / IEEE; 2015:1078-1083. doi:10.7873/DATE.2015.1124
LibreCat: /record/238
DOI: 10.7873/DATE.2015.1124

Meisner S, Platzner M. Thread Shadowing: Using Dynamic Redundancy on Hybrid Multi-cores for Error Detection. In: Goehringer D, Santambrogio M, Cardoso JP, Bertels K, eds. Proceedings of the 10th International Symposium on Applied Reconfigurable Computing (ARC). Lecture Notes in Computer Science. Springer; 2014:283-290. doi:10.1007/978-3-319-05960-0_30
LibreCat: /record/347
DOI: 10.1007/978-3-319-05960-0_30

Graf T, Schaefers L, Platzner M. On Semeai Detection in Monte-Carlo Go. In: Proc. Conf. on Computers and Games (CG). Lecture Notes in Computer Science. Switzerland: Springer; 2014:14-25. doi:10.1007/978-3-319-09165-5_2
LibreCat: /record/1782
DOI: 10.1007/978-3-319-09165-5_2

Wiersema T, Drzevitzky S, Platzner M. Memory Security in Reconfigurable Computers: Combining Formal Verification with Monitoring. In: Proceedings of the International Conference on Field-Programmable Technology (FPT). ; 2014:167-174. doi:10.1109/FPT.2014.7082771
LibreCat: /record/399
DOI: 10.1109/FPT.2014.7082771

Jakobs M-C, Platzner M, Wiersema T, Wehrheim H. Integrating Software and Hardware Verification. In: Albert E, Sekerinski E, eds. Proceedings of the 11th International Conference on Integrated Formal Methods (IFM). LNCS. ; 2014:307-322. doi:10.1007/978-3-319-10181-1_19
LibreCat: /record/408
DOI: 10.1007/978-3-319-10181-1_19

Wiersema T, Bockhorn A, Platzner M. Embedding FPGA Overlays into Configurable Systems-on-Chip: ReconOS meets ZUMA. In: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig). ; 2014:1-6. doi:10.1109/ReConFig.2014.7032514
LibreCat: /record/433
DOI: 10.1109/ReConFig.2014.7032514

Schaefers L, Platzner M. A Novel Technique and its Application to Computer Go. IEEE Transactions on Computational Intelligence and AI in Games. 2014;6(3):361-374. doi:10.1109/TCIAIG.2014.2346997
LibreCat: /record/10602
DOI: 10.1109/TCIAIG.2014.2346997

Giefers H, Platzner M. An FPGA-based Reconfigurable Mesh Many-Core. IEEE Transactions on Computers. 2014;63(12):2919-2932. doi:10.1109/TC.2013.174
LibreCat: /record/10603
DOI: 10.1109/TC.2013.174

Anwer J, Platzner M, Meisner S. FPGA Redundancy Configurations: An Automated Design Space Exploration. In: Reconfigurable Architectures Workshop (RAW). RAW. ; 2014. doi:10.1109/IPDPSW.2014.37
LibreCat: /record/10621
DOI: 10.1109/IPDPSW.2014.37

Bockhorn A. Echtzeit Klassifikation von SEMG Signalen Mit Einem Low-Cost DSP Evaluation Board. Paderborn University; 2014.
LibreCat: /record/10627

Boschmann A, Platzner M. A computer vision-based approach to high density EMG pattern recognition using structural similarity. In: Proc. MyoElectric Controls Symposium (MEC). ; 2014.
LibreCat: /record/10632

Boschmann A, Platzner M. Towards robust HD EMG pattern recognition: Reducing electrode displacement effect using structural similarity. In: Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC). ; 2014.
LibreCat: /record/10633

Brand M. A Generalized Loop Accelerator Implemented as a Coarse-Grained Array. Paderborn University; 2014.
LibreCat: /record/10640

Damschen M. Easy-to-Use-on-the-Fly Binary Program Acceleration on Many-Cores. Paderborn University; 2014.
LibreCat: /record/10645

Glette K, Kaufmann P. Lookup Table Partial Reconfiguration for an Evolvable Hardware Classifier System. In: IEEE Congress on Evolutionary Computation (CEC). ; 2014.
LibreCat: /record/10654

Hagedorn C. Entwicklung Einer Codegrößenoptimierten Softwarebibliothek Für 8-Bit Mikrocontroller in Netzunabhängigen Notleuchten. Paderborn University; 2014.
LibreCat: /record/10665

Ho N, Kaufmann P, Platzner M. A hardware/software infrastructure for performance monitoring on LEON3 multicore platforms. In: 24th Intl. Conf. on Field Programmable Logic and Applications (FPL). ; 2014:1-4. doi:10.1109/FPL.2014.6927437
LibreCat: /record/10674
DOI: 10.1109/FPL.2014.6927437

Ho N, Kaufmann P, Platzner M. Towards self-adaptive caches: A run-time reconfigurable multi-core infrastructure. In: 2014 IEEE Intl. Conf. on Evolvable Systems (ICES). ; 2014:31-37. doi:10.1109/ICES.2014.7008719
LibreCat: /record/10677
DOI: 10.1109/ICES.2014.7008719

König F. EMG-Basierte Simultane Und Proportionale Online-Steuerung Einer Virtuellen Prothese. Paderborn University; 2014.
LibreCat: /record/10679

Koch B. Hardware Acceleration of Mechatronic Controllers on a Zynq Platform FPGA. Paderborn University; 2014.
LibreCat: /record/10701

Mittendorf R. Advanced AES-Key Recovery from Decayed RAM Using Multi-Threading and FPGAs. Paderborn University; 2014.
LibreCat: /record/10715

Rüthing C. The Xilinx Zynq Architecture as a Platform for Reconfigurable Heterogeneous Multi-Cores. Paderborn University; 2014.
LibreCat: /record/10732

Schäfers L. Parallel Monte-Carlo Tree Search for HPC Systems and Its Application to Computer Go. Berlin: Logos Verlag Berlin GmbH; 2014.
LibreCat: /record/10733

Shen C, Kaufmann P, Braun M. Optimizing the Generator Start-up Sequence After a Power System Blackout. In: IEEE Power and Energy Society General Meeting (IEEE GM). ; 2014.
LibreCat: /record/10738

Shen C, Kaufmann P, Braun M. A New Distribution Network Reconfiguration and Restoration Path Selection Algorithm. In: Power Systems Computation Conference (PSCC). IEEE; 2014.
LibreCat: /record/10739

Surmund S. Multithreaded Parallelization of Mechatronic Controllers on a Zynq Platform FPGA. Paderborn University; 2014.
LibreCat: /record/10744

I. Esparcia-Alc\rquote azar A, Eiben AE, Agapitos A, et al. Applications of Evolutionary Computation - 17th European Conference, EvoApplications. Vol 8602. Granada, Spain: Springer; 2014.
LibreCat: /record/10756

Anwer J, Platzner M. Analytic reliability evaluation for fault-tolerant circuit structures on FPGAs. In: IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT). IEEE; 2014:177-184. doi:10.1109/DFT.2014.6962108
LibreCat: /record/10764
DOI: 10.1109/DFT.2014.6962108

Ghasemzadeh Mohammadi H, Gaillardon P-E, Yazdani M, De Micheli G. Fast process variation analysis in nano-scaled technologies using column-wise sparse parameter selection. In: 2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH). IEEE; 2014:163-168. doi:10.1109/NANOARCH.2014.6880479
LibreCat: /record/10773
DOI: 10.1109/NANOARCH.2014.6880479

Graf T, Platzner M. Common Fate Graph Patterns in Monte Carlo Tree Search for Computer Go. In: 2014 IEEE Conference on Computational Intelligence and Games. ; 2014:1-8. doi:10.1109/CIG.2014.6932863
LibreCat: /record/13154
DOI: 10.1109/CIG.2014.6932863

Platzner M, Plessl C. Verschiebungen an der Grenze zwischen Hardware und Software. In: Künsemöller J, Eke NO, Foit L, Kaerlein T, eds. Logiken strukturbildender Prozesse: Automatismen. Schriftenreihe des Graduiertenkollegs “Automatismen.” Wilhelm Fink; 2014:123-144.
LibreCat: /record/335

Kenter T, Vaz GF, Plessl C. Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer. In: Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC). Vol 8405. Lecture Notes in Computer Science (LNCS). Springer International Publishing; 2014:144-155. doi:10.1007/978-3-319-05960-0_13
LibreCat: /record/388
DOI: 10.1007/978-3-319-05960-0_13

Agne A, Hangmann H, Happe M, Platzner M, Plessl C. Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators. Microprocessors and Microsystems. 2014;38(8, Part B):911-919. doi:10.1016/j.micpro.2013.12.001
LibreCat: /record/363
DOI: 10.1016/j.micpro.2013.12.001

Riebler H, Kenter T, Plessl C, Sorge C. Reconstructing AES Key Schedules from Decayed Memory with FPGAs. In: Proceedings of Field-Programmable Custom Computing Machines (FCCM). IEEE; 2014:222-229. doi:10.1109/FCCM.2014.67
LibreCat: /record/377
DOI: 10.1109/FCCM.2014.67

Agne A, Happe M, Lösch A, Plessl C, Platzner M. Self-awareness as a Model for Designing and Operating Heterogeneous Multicores. ACM Transactions on Reconfigurable Technology and Systems (TRETS). 2014;7(2). doi:10.1145/2617596
LibreCat: /record/365
DOI: 10.1145/2617596

Agne A, Happe M, Keller A, et al. ReconOS - An Operating System Approach for Reconfigurable Computing. IEEE Micro. 2014;34(1):60-71. doi:10.1109/MM.2013.110
LibreCat: /record/328
DOI: 10.1109/MM.2013.110

C. Durelli G, Pogliani M, Miele A, et al. Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach. In: Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA). IEEE; 2014:142-149. doi:10.1109/ISPA.2014.27
LibreCat: /record/1778
DOI: 10.1109/ISPA.2014.27

Vaz GF, Riebler H, Kenter T, Plessl C. Deferring Accelerator Offloading Decisions to Application Runtime. In: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE; 2014:1-8. doi:10.1109/ReConFig.2014.7032509
LibreCat: /record/439
DOI: 10.1109/ReConFig.2014.7032509

Kenter T, Schmitz H, Plessl C. Kernel-Centric Acceleration of High Accuracy Stereo-Matching. In: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE; 2014:1-8. doi:10.1109/ReConFig.2014.7032535
LibreCat: /record/406
DOI: 10.1109/ReConFig.2014.7032535

C. Durelli G, Copolla M, Djafarian K, et al. SAVE: Towards efficient resource management in heterogeneous system architectures. In: Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC). Springer; 2014. doi:10.1007/978-3-319-05960-0_38
LibreCat: /record/1780
DOI: 10.1007/978-3-319-05960-0_38

Giefers H, Plessl C, Förstner J. Accelerating Finite Difference Time Domain Simulations with Reconfigurable Dataflow Computers. ACM SIGARCH Computer Architecture News. 2014;41(5):65-70. doi:10.1145/2641361.2641372
LibreCat: /record/1779
DOI: 10.1145/2641361.2641372

Kaufmann P. Adapting Hardware Systems by Means of Multi-Objective Evolution. Berlin: Logos Verlag Berlin GmbH; 2013.
LibreCat: /record/11619

Kasap S, Redif S. FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm. In: Proc. IEEE Signal Processing and Communications Conf. (SUI). IEEE; 2013. doi:10.1109/SIU.2013.6531530
LibreCat: /record/1786
DOI: 10.1109/SIU.2013.6531530

Kasap S, Redif S. Novel Field-Programmable Gate Array Architecture for Computing the Eigenvalue Decomposition of Para-Hermitian Polynomial Matrices. IEEE Trans on Very Large Scale Integration (VLSI) Systems. 2013;22(3):522-536. doi:10.1109/TVLSI.2013.2248069
LibreCat: /record/1792
DOI: 10.1109/TVLSI.2013.2248069

Happe M. Performance and Thermal Management on Self-Adaptive Hybrid Multi-Cores. Berlin: Logos Verlag Berlin GmbH; 2013.
LibreCat: /record/501

Happe M, Lübbers E, Platzner M. A Self-adaptive Heterogeneous Multi-core Architecture for Embedded Real-time Video Object Tracking. International Journal of Real-time Image Processing. 2013;8(1):95-110. doi:doi:10.1007/s11554-011-0212-y
LibreCat: /record/10604
DOI: doi:10.1007/s11554-011-0212-y

Anwer J, Meisner S, Platzner M. Dynamic reliability management: Reconfiguring reliability-levels of hardware designs at runtime. In: Reconfigurable Computing and FPGAs (ReConFig), 2013 International Conference On. ; 2013:1-6. doi:10.1109/ReConFig.2013.6732280
LibreCat: /record/10620
DOI: 10.1109/ReConFig.2013.6732280

Bick C. Beschleunigung von Tiefenberechnung Aus Stereobildern Durch FPGA-Basierte Datenflussrechner. Paderborn University; 2013.
LibreCat: /record/10626

Boschmann A, Nofen B, Platzner M. Improving transient state myoelectric signal recognition in hand movement classification using gyroscopes. In: Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC). ; 2013.
LibreCat: /record/10634

Boschmann A, Platzner M. Reducing the limb position effect in pattern recognition based myoelectric control using a high density electrode array. In: Proc. IEEE ISSNIP Biosignals and Biorobotics Conference (BRC). ; 2013.
LibreCat: /record/10635

Glette K, Kaufmann P, Assad C, Wolf M. Investigating Evolvable Hardware Classification for the BioSleeve Electromyographic Interface. In: IEEE Intl. Conf. on Evolvable Systems (ICES). Vol 1. LNCS. Springer; 2013:1-1.
LibreCat: /record/10655

Kaufmann P. Adapting Hardware Systems by Means of Multi-Objective Evolution. Berlin: Logos Verlag; 2013.
LibreCat: /record/10681

Kaufmann P, Glette K, Gruber T, Platzner M, Torresen J, Sick B. Classification of Electromyographic Signals: Comparing Evolvable Hardware to Conventional Classifiers. IEEE Transactions on Evolutionary Computation. 2013;17(1):46-63. doi:10.1109/TEVC.2012.2185845
LibreCat: /record/10684
DOI: 10.1109/TEVC.2012.2185845

Knoop M. Behavior Models for Electric Vehicles. IWES Kassel; 2013.
LibreCat: /record/10700

Nofen B. Verbesserung Der Erkennungsrate Eines Systems Zur Klassifikation von EMG-Signalen Durch Den Einsatz Eines Hybriden Lagesensors. Paderborn University; 2013.
LibreCat: /record/10720

Pudelko D. Überquerung Der Styx - Betriebsparametervariation Und Fehlerverhalten Eines Platform FPGAs. Paderborn University; 2013.
LibreCat: /record/10727

Riebler H. Identifikation Und Wiederherstellung von Kryptographischen Schlüsseln Mit FPGAs. Paderborn University; 2013.
LibreCat: /record/10730

Sprenger A. MiBenchHybridf: Erweiterung Eines Benchmarks Um Hardwarebeschleunigung. Paderborn University; 2013.
LibreCat: /record/10741

Steppeler P. Beschleunigung von Einzelbild-Erkennungsverfahren Auf Datenfluss Basierenden HPC Systemen. Paderborn University; 2013.
LibreCat: /record/10743

Toebermann C, Geibel D, Hau M, et al. Real-Time Simulation of Distribution Grids with high Penetration of Regenerative and Distributed Generation. In: Real-Time Conference. OPAL RT Paris; 2013.
LibreCat: /record/10745

Ghasemzadeh Mohammadi H, Gaillardon P-E, Yazdani M, De Micheli G. A fast TCAD-based methodology for Variation analysis of emerging nano-devices. In: 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS). IEEE; 2013:83-88. doi:10.1109/DFT.2013.6653587
LibreCat: /record/10774
DOI: 10.1109/DFT.2013.6653587

Gaillardon P-E, Ghasemzadeh Mohammadi H, De Micheli G. Vertically-stacked silicon nanowire transistors with controllable polarity: A robustness study. In: 2013 14th Latin American Test Workshop-LATW. IEEE; 2013:1-6. doi:10.1109/LATW.2013.6562673
LibreCat: /record/10775
DOI: 10.1109/LATW.2013.6562673

Graf T, Schäfers L, Platzner M. On Semeai Detection in Monte-Carlo Go. In: Proceedings of the International Conference on Computers and Games (CG). Springer; 2013.
LibreCat: /record/13645

Riebler H, Kenter T, Sorge C, Plessl C. FPGA-accelerated Key Search for Cold-Boot Attacks against AES. In: Proceedings of the International Conference on Field-Programmable Technology (FPT). IEEE; 2013:386-389. doi:10.1109/FPT.2013.6718394
LibreCat: /record/528
DOI: 10.1109/FPT.2013.6718394

Happe M, Kling P, Plessl C, Platzner M, Meyer auf der Heide F. On-The-Fly Computing: A Novel Paradigm for Individualized IT Services. In: Proceedings of the 9th IEEE Workshop on Software Technology for Future Embedded and Ubiquitous Systems (SEUS). IEEE; 2013. doi:10.1109/ISORC.2013.6913232
LibreCat: /record/505
DOI: 10.1109/ISORC.2013.6913232

Suess T, Schoenrock A, Meisner S, Plessl C. Parallel Macro Pipelining on the Intel SCC Many-Core Computer. In: Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW). IEEE Computer Society; 2013:64-73. doi:10.1109/IPDPSW.2013.136
LibreCat: /record/1787
DOI: 10.1109/IPDPSW.2013.136

Kasap S, Redif S. FPGA-based design and implementation of an approximate polynomial matrix EVD algorithm. In: Proc. Int. Conf. on Field Programmable Technology (ICFPT). IEEE Computer Society; 2012:135-140. doi:10.1109/FPT.2012.6412125
LibreCat: /record/2097
DOI: 10.1109/FPT.2012.6412125

Kasap S, Redif S. FPGA implementation of a second-order convolutive blind signal separation algorithm. In: Int. Architecture and Engineering Symp. (ARCHENG). ; 2012.
LibreCat: /record/2100

Wistuba M, Schaefers L, Platzner M. Comparison of Bayesian Move Prediction Systems for Computer Go. In: Proc. IEEE Conf. on Computational Intelligence and Games (CIG). IEEE; 2012:91-99. doi:10.1109/CIG.2012.6374143
LibreCat: /record/2103
DOI: 10.1109/CIG.2012.6374143

Thielemans K, Tsoumpas C, Mustafovic S, et al. STIR: Software for Tomographic Image Reconstruction Release 2. Physics in Medicine and Biology. 2012;57(4):867-883. doi:10.1088/0031-9155/57/4/867
LibreCat: /record/2172
DOI: 10.1088/0031-9155/57/4/867

Redif S, Kasap S. Parallel algorithm for computation of second-order sequential best rotations. Int Journal of Electronics. 2012;100(12):1646-1651. doi:10.1080/00207217.2012.751343
LibreCat: /record/2173
DOI: 10.1080/00207217.2012.751343

Kasap S, Benkrid K. Parallel Processor Design and Implementation for Molecular Dynamics Simulations on a FPGA Parallel Computer. Journal of Computers. 2012;7(6):1312-1328.
LibreCat: /record/2174

Drzevitzky S. Proof-Carrying Hardware: A Novel Approach to Reconfigurable Hardware Security. Universität Paderborn; 2012.
LibreCat: /record/586

Plessl C, Platzner M, Agne A, Happe M, Lübbers E. Programming Models for Reconfigurable Heterogeneous Multi-Cores. Awareness Magazine; 2012.
LibreCat: /record/587

Boschmann A, Platzner M. Reducing classification accuracy degradation of pattern recognition based myoelectric control caused by electrode shift using a high density electrode array. In: Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC). ; 2012.
LibreCat: /record/10636

Dridger D. Design and Implementation of a Nanophotonics Simulation Personality for the Convey HC-1 Hybrid Core Computer. Paderborn University; 2012.
LibreCat: /record/10650

Giefers H. Design and Programming of Reconfigurable Mesh Based Many-Cores. Berlin: Logos Verlag Berlin GmbH; 2012.
LibreCat: /record/10652

Graf T. Adaptive Playouts in Der Monte-Carlo Spielbaumsuche Am Anwendungsfall Go. Paderborn University; 2012.
LibreCat: /record/10658

Hangmann H. Generating Adjustable Temperature Gradients on Modern FPGAs. Paderborn University; 2012.
LibreCat: /record/10667

Kaufmann P, Glette K, Platzner M, Torresen J. Compensating Resource Fluctuations by Means of Evolvable Hardware: The Run-Time Reconfigurable Functional Unit Row Classifier Architecture. International Journal of Adaptive, Resilient and Autonomic Systems (IJARAS). 2012;3(4):17-31. doi:10.4018/jaras.2012100102
LibreCat: /record/10685
DOI: 10.4018/jaras.2012100102

Platzner M, Boschmann A, Kaufmann P. Wieder Natürlich Gehen Und Greifen.; 2012:6-11.
LibreCat: /record/10723

Schmitz H. Stereo Matching on a HC-1 Hybrid Core Computer. Paderborn University; 2012.
LibreCat: /record/10734

Topmöller C. Entwicklung Eines Picoblaze Compilers Mit Dem Gentle Compiler Construction System. Paderborn University; 2012.
LibreCat: /record/10747

Wistuba M. Analysis of Pattern Based Model Design and Learning in Computer-Go. Paderborn University; 2012.
LibreCat: /record/10754