Anwer J, Platzner M. Analytic reliability evaluation for fault-tolerant circuit structures on FPGAs. In: IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT). IEEE; 2014:177-184. doi:10.1109/DFT.2014.6962108
LibreCat: /record/10764
DOI: 10.1109/DFT.2014.6962108

Ghasemzadeh Mohammadi H, Gaillardon P-E, Yazdani M, De Micheli G. Fast process variation analysis in nano-scaled technologies using column-wise sparse parameter selection. In: 2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH). IEEE; 2014:163-168. doi:10.1109/NANOARCH.2014.6880479
LibreCat: /record/10773
DOI: 10.1109/NANOARCH.2014.6880479

Graf T, Platzner M. Common Fate Graph Patterns in Monte Carlo Tree Search for Computer Go. In: 2014 IEEE Conference on Computational Intelligence and Games. ; 2014:1-8. doi:10.1109/CIG.2014.6932863
LibreCat: /record/13154
DOI: 10.1109/CIG.2014.6932863

Platzner M, Plessl C. Verschiebungen an der Grenze zwischen Hardware und Software. In: Künsemöller J, Eke NO, Foit L, Kaerlein T, eds. Logiken strukturbildender Prozesse: Automatismen. Schriftenreihe des Graduiertenkollegs “Automatismen.” Wilhelm Fink; 2014:123-144.
LibreCat: /record/335

Kenter T, Vaz GF, Plessl C. Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer. In: Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC). Vol 8405. Lecture Notes in Computer Science (LNCS). Springer International Publishing; 2014:144-155. doi:10.1007/978-3-319-05960-0_13
LibreCat: /record/388
DOI: 10.1007/978-3-319-05960-0_13

Agne A, Hangmann H, Happe M, Platzner M, Plessl C. Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators. Microprocessors and Microsystems. 2014;38(8, Part B):911-919. doi:10.1016/j.micpro.2013.12.001
LibreCat: /record/363
DOI: 10.1016/j.micpro.2013.12.001

Riebler H, Kenter T, Plessl C, Sorge C. Reconstructing AES Key Schedules from Decayed Memory with FPGAs. In: Proceedings of Field-Programmable Custom Computing Machines (FCCM). IEEE; 2014:222-229. doi:10.1109/FCCM.2014.67
LibreCat: /record/377
DOI: 10.1109/FCCM.2014.67

Agne A, Happe M, Lösch A, Plessl C, Platzner M. Self-awareness as a Model for Designing and Operating Heterogeneous Multicores. ACM Transactions on Reconfigurable Technology and Systems (TRETS). 2014;7(2). doi:10.1145/2617596
LibreCat: /record/365
DOI: 10.1145/2617596

Agne A, Happe M, Keller A, et al. ReconOS - An Operating System Approach for Reconfigurable Computing. IEEE Micro. 2014;34(1):60-71. doi:10.1109/MM.2013.110
LibreCat: /record/328
DOI: 10.1109/MM.2013.110

C. Durelli G, Pogliani M, Miele A, et al. Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach. In: Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA). IEEE; 2014:142-149. doi:10.1109/ISPA.2014.27
LibreCat: /record/1778
DOI: 10.1109/ISPA.2014.27

Vaz GF, Riebler H, Kenter T, Plessl C. Deferring Accelerator Offloading Decisions to Application Runtime. In: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE; 2014:1-8. doi:10.1109/ReConFig.2014.7032509
LibreCat: /record/439
DOI: 10.1109/ReConFig.2014.7032509

Kenter T, Schmitz H, Plessl C. Kernel-Centric Acceleration of High Accuracy Stereo-Matching. In: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE; 2014:1-8. doi:10.1109/ReConFig.2014.7032535
LibreCat: /record/406
DOI: 10.1109/ReConFig.2014.7032535

C. Durelli G, Copolla M, Djafarian K, et al. SAVE: Towards efficient resource management in heterogeneous system architectures. In: Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC). Springer; 2014. doi:10.1007/978-3-319-05960-0_38
LibreCat: /record/1780
DOI: 10.1007/978-3-319-05960-0_38

Giefers H, Plessl C, Förstner J. Accelerating Finite Difference Time Domain Simulations with Reconfigurable Dataflow Computers. ACM SIGARCH Computer Architecture News. 2014;41(5):65-70. doi:10.1145/2641361.2641372
LibreCat: /record/1779
DOI: 10.1145/2641361.2641372

Kaufmann P. Adapting Hardware Systems by Means of Multi-Objective Evolution. Berlin: Logos Verlag Berlin GmbH; 2013.
LibreCat: /record/11619

Kasap S, Redif S. FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm. In: Proc. IEEE Signal Processing and Communications Conf. (SUI). IEEE; 2013. doi:10.1109/SIU.2013.6531530
LibreCat: /record/1786
DOI: 10.1109/SIU.2013.6531530

Kasap S, Redif S. Novel Field-Programmable Gate Array Architecture for Computing the Eigenvalue Decomposition of Para-Hermitian Polynomial Matrices. IEEE Trans on Very Large Scale Integration (VLSI) Systems. 2013;22(3):522-536. doi:10.1109/TVLSI.2013.2248069
LibreCat: /record/1792
DOI: 10.1109/TVLSI.2013.2248069

Happe M. Performance and Thermal Management on Self-Adaptive Hybrid Multi-Cores. Berlin: Logos Verlag Berlin GmbH; 2013.
LibreCat: /record/501

Happe M, Lübbers E, Platzner M. A Self-adaptive Heterogeneous Multi-core Architecture for Embedded Real-time Video Object Tracking. International Journal of Real-time Image Processing. 2013;8(1):95-110. doi:doi:10.1007/s11554-011-0212-y
LibreCat: /record/10604
DOI: doi:10.1007/s11554-011-0212-y

Anwer J, Meisner S, Platzner M. Dynamic reliability management: Reconfiguring reliability-levels of hardware designs at runtime. In: Reconfigurable Computing and FPGAs (ReConFig), 2013 International Conference On. ; 2013:1-6. doi:10.1109/ReConFig.2013.6732280
LibreCat: /record/10620
DOI: 10.1109/ReConFig.2013.6732280

Bick C. Beschleunigung von Tiefenberechnung Aus Stereobildern Durch FPGA-Basierte Datenflussrechner. Paderborn University; 2013.
LibreCat: /record/10626

Boschmann A, Nofen B, Platzner M. Improving transient state myoelectric signal recognition in hand movement classification using gyroscopes. In: Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC). ; 2013.
LibreCat: /record/10634

Boschmann A, Platzner M. Reducing the limb position effect in pattern recognition based myoelectric control using a high density electrode array. In: Proc. IEEE ISSNIP Biosignals and Biorobotics Conference (BRC). ; 2013.
LibreCat: /record/10635

Glette K, Kaufmann P, Assad C, Wolf M. Investigating Evolvable Hardware Classification for the BioSleeve Electromyographic Interface. In: IEEE Intl. Conf. on Evolvable Systems (ICES). Vol 1. LNCS. Springer; 2013:1-1.
LibreCat: /record/10655

Kaufmann P. Adapting Hardware Systems by Means of Multi-Objective Evolution. Berlin: Logos Verlag; 2013.
LibreCat: /record/10681

Kaufmann P, Glette K, Gruber T, Platzner M, Torresen J, Sick B. Classification of Electromyographic Signals: Comparing Evolvable Hardware to Conventional Classifiers. IEEE Transactions on Evolutionary Computation. 2013;17(1):46-63. doi:10.1109/TEVC.2012.2185845
LibreCat: /record/10684
DOI: 10.1109/TEVC.2012.2185845

Knoop M. Behavior Models for Electric Vehicles. IWES Kassel; 2013.
LibreCat: /record/10700

Nofen B. Verbesserung Der Erkennungsrate Eines Systems Zur Klassifikation von EMG-Signalen Durch Den Einsatz Eines Hybriden Lagesensors. Paderborn University; 2013.
LibreCat: /record/10720

Pudelko D. Überquerung Der Styx - Betriebsparametervariation Und Fehlerverhalten Eines Platform FPGAs. Paderborn University; 2013.
LibreCat: /record/10727

Riebler H. Identifikation Und Wiederherstellung von Kryptographischen Schlüsseln Mit FPGAs. Paderborn University; 2013.
LibreCat: /record/10730

Sprenger A. MiBenchHybridf: Erweiterung Eines Benchmarks Um Hardwarebeschleunigung. Paderborn University; 2013.
LibreCat: /record/10741

Steppeler P. Beschleunigung von Einzelbild-Erkennungsverfahren Auf Datenfluss Basierenden HPC Systemen. Paderborn University; 2013.
LibreCat: /record/10743

Toebermann C, Geibel D, Hau M, et al. Real-Time Simulation of Distribution Grids with high Penetration of Regenerative and Distributed Generation. In: Real-Time Conference. OPAL RT Paris; 2013.
LibreCat: /record/10745

Ghasemzadeh Mohammadi H, Gaillardon P-E, Yazdani M, De Micheli G. A fast TCAD-based methodology for Variation analysis of emerging nano-devices. In: 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS). IEEE; 2013:83-88. doi:10.1109/DFT.2013.6653587
LibreCat: /record/10774
DOI: 10.1109/DFT.2013.6653587

Gaillardon P-E, Ghasemzadeh Mohammadi H, De Micheli G. Vertically-stacked silicon nanowire transistors with controllable polarity: A robustness study. In: 2013 14th Latin American Test Workshop-LATW. IEEE; 2013:1-6. doi:10.1109/LATW.2013.6562673
LibreCat: /record/10775
DOI: 10.1109/LATW.2013.6562673

Graf T, Schäfers L, Platzner M. On Semeai Detection in Monte-Carlo Go. In: Proceedings of the International Conference on Computers and Games (CG). Springer; 2013.
LibreCat: /record/13645

Riebler H, Kenter T, Sorge C, Plessl C. FPGA-accelerated Key Search for Cold-Boot Attacks against AES. In: Proceedings of the International Conference on Field-Programmable Technology (FPT). IEEE; 2013:386-389. doi:10.1109/FPT.2013.6718394
LibreCat: /record/528
DOI: 10.1109/FPT.2013.6718394

Happe M, Kling P, Plessl C, Platzner M, Meyer auf der Heide F. On-The-Fly Computing: A Novel Paradigm for Individualized IT Services. In: Proceedings of the 9th IEEE Workshop on Software Technology for Future Embedded and Ubiquitous Systems (SEUS). IEEE; 2013. doi:10.1109/ISORC.2013.6913232
LibreCat: /record/505
DOI: 10.1109/ISORC.2013.6913232

Suess T, Schoenrock A, Meisner S, Plessl C. Parallel Macro Pipelining on the Intel SCC Many-Core Computer. In: Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW). IEEE Computer Society; 2013:64-73. doi:10.1109/IPDPSW.2013.136
LibreCat: /record/1787
DOI: 10.1109/IPDPSW.2013.136

Kasap S, Redif S. FPGA-based design and implementation of an approximate polynomial matrix EVD algorithm. In: Proc. Int. Conf. on Field Programmable Technology (ICFPT). IEEE Computer Society; 2012:135-140. doi:10.1109/FPT.2012.6412125
LibreCat: /record/2097
DOI: 10.1109/FPT.2012.6412125

Kasap S, Redif S. FPGA implementation of a second-order convolutive blind signal separation algorithm. In: Int. Architecture and Engineering Symp. (ARCHENG). ; 2012.
LibreCat: /record/2100

Wistuba M, Schaefers L, Platzner M. Comparison of Bayesian Move Prediction Systems for Computer Go. In: Proc. IEEE Conf. on Computational Intelligence and Games (CIG). IEEE; 2012:91-99. doi:10.1109/CIG.2012.6374143
LibreCat: /record/2103
DOI: 10.1109/CIG.2012.6374143

Thielemans K, Tsoumpas C, Mustafovic S, et al. STIR: Software for Tomographic Image Reconstruction Release 2. Physics in Medicine and Biology. 2012;57(4):867-883. doi:10.1088/0031-9155/57/4/867
LibreCat: /record/2172
DOI: 10.1088/0031-9155/57/4/867

Redif S, Kasap S. Parallel algorithm for computation of second-order sequential best rotations. Int Journal of Electronics. 2012;100(12):1646-1651. doi:10.1080/00207217.2012.751343
LibreCat: /record/2173
DOI: 10.1080/00207217.2012.751343

Kasap S, Benkrid K. Parallel Processor Design and Implementation for Molecular Dynamics Simulations on a FPGA Parallel Computer. Journal of Computers. 2012;7(6):1312-1328.
LibreCat: /record/2174

Drzevitzky S. Proof-Carrying Hardware: A Novel Approach to Reconfigurable Hardware Security. Universität Paderborn; 2012.
LibreCat: /record/586

Plessl C, Platzner M, Agne A, Happe M, Lübbers E. Programming Models for Reconfigurable Heterogeneous Multi-Cores. Awareness Magazine; 2012.
LibreCat: /record/587

Boschmann A, Platzner M. Reducing classification accuracy degradation of pattern recognition based myoelectric control caused by electrode shift using a high density electrode array. In: Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC). ; 2012.
LibreCat: /record/10636

Dridger D. Design and Implementation of a Nanophotonics Simulation Personality for the Convey HC-1 Hybrid Core Computer. Paderborn University; 2012.
LibreCat: /record/10650

Giefers H. Design and Programming of Reconfigurable Mesh Based Many-Cores. Berlin: Logos Verlag Berlin GmbH; 2012.
LibreCat: /record/10652

Graf T. Adaptive Playouts in Der Monte-Carlo Spielbaumsuche Am Anwendungsfall Go. Paderborn University; 2012.
LibreCat: /record/10658

Hangmann H. Generating Adjustable Temperature Gradients on Modern FPGAs. Paderborn University; 2012.
LibreCat: /record/10667

Kaufmann P, Glette K, Platzner M, Torresen J. Compensating Resource Fluctuations by Means of Evolvable Hardware: The Run-Time Reconfigurable Functional Unit Row Classifier Architecture. International Journal of Adaptive, Resilient and Autonomic Systems (IJARAS). 2012;3(4):17-31. doi:10.4018/jaras.2012100102
LibreCat: /record/10685
DOI: 10.4018/jaras.2012100102

Platzner M, Boschmann A, Kaufmann P. Wieder Natürlich Gehen Und Greifen.; 2012:6-11.
LibreCat: /record/10723

Schmitz H. Stereo Matching on a HC-1 Hybrid Core Computer. Paderborn University; 2012.
LibreCat: /record/10734

Topmöller C. Entwicklung Eines Picoblaze Compilers Mit Dem Gentle Compiler Construction System. Paderborn University; 2012.
LibreCat: /record/10747

Wistuba M. Analysis of Pattern Based Model Design and Learning in Computer-Go. Paderborn University; 2012.
LibreCat: /record/10754

Lewis P, Platzner M, Yao X. An Outlook for Self-Awareness in Computing Systems. Awareness Magazine; 2012.
LibreCat: /record/13462

Meyer B, Schumacher J, Plessl C, Förstner J. Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort? In: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL). IEEE; 2012:189-196. doi:10.1109/FPL.2012.6339370
LibreCat: /record/2106
DOI: 10.1109/FPL.2012.6339370

Schumacher T, Plessl C, Platzner M. IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators. Microprocessors and Microsystems. 2012;36(2):110-126. doi:10.1016/j.micpro.2011.04.002
LibreCat: /record/2108
DOI: 10.1016/j.micpro.2011.04.002

Happe M, Hangmann H, Agne A, Plessl C. Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators. In: Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig). IEEE; 2012:1-8. doi:10.1109/ReConFig.2012.6416745
LibreCat: /record/615
DOI: 10.1109/ReConFig.2012.6416745

Kenter T, Plessl C, Schmitz H. Pragma based parallelization - Trading hardware efficiency for ease of use? In: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE; 2012:1-8. doi:10.1109/ReConFig.2012.6416773
LibreCat: /record/591
DOI: 10.1109/ReConFig.2012.6416773

Happe M, Agne A, Plessl C, Platzner M. Hardware/Software Platform for Self-aware Compute Nodes. In: Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS). ; 2012:8-9.
LibreCat: /record/609

Barrio P, Carreras C, Sierra R, Kenter T, Plessl C. Turning control flow graphs into function calls: Code generation for heterogeneous architectures. In: Proceedings of the International Conference on High Performance Computing and Simulation (HPCS). IEEE; 2012:559-565. doi:10.1109/HPCSim.2012.6266973
LibreCat: /record/567
DOI: 10.1109/HPCSim.2012.6266973

Rüthing C, Happe M, Agne A, Plessl C. Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs. In: Proceedings of the International Conference on Field Programmable Logic and Applications (FPL). IEEE; 2012:559-562. doi:10.1109/FPL.2012.6339370
LibreCat: /record/612
DOI: 10.1109/FPL.2012.6339370

Beisel T, Wiersema T, Plessl C, Brinkmann A. Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux. In: Proc. Workshop on Computer Architecture and Operating System Co-Design (CAOS). ; 2012.
LibreCat: /record/2180

Grad M, Plessl C. On the Feasibility and Limitations of Just-In-Time Instruction Set Extension for FPGA-based Reconfigurable Processors. Int Journal of Reconfigurable Computing (IJRC). Published online 2012. doi:10.1155/2012/418315
LibreCat: /record/2177
DOI: 10.1155/2012/418315

Kenter T, Plessl C, Platzner M, Kauschke M. Estimation and Partitioning for CPU-Accelerator Architectures. In: Intel European Research and Innovation Conference. ; 2011.
LibreCat: /record/2191

Plessl C, Platzner M. Hardware Virtualization on Dynamically Reconfigurable Embedded Processors. In: Khalgui M, Hanisch H-M, eds. Reconfigurable Embedded Control Systems: Applications for Flexibility and Agility. Hershey, PA, USA: IGI Global; 2011. doi:10.4018/978-1-60960-086-0
LibreCat: /record/2202
DOI: 10.4018/978-1-60960-086-0

Graf T, Lorenz U, Platzner M, Schaefers L. Parallel Monte-Carlo Tree Search for HPC Systems. In: Proc. European Conf. on Parallel Processing (Euro-Par). Vol 6853. Lecture Notes in Computer Science (LNCS). Berlin / Heidelberg: Springer; 2011. doi:10.1007/978-3-642-23397-5_36
LibreCat: /record/2204
DOI: 10.1007/978-3-642-23397-5_36

Drzevitzky S, Platzner M. Achieving Hardware Security for Reconû01gurable Systems on Chip by a Proof-Carrying Code Approach. In: Proceedings of the 6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC). ; 2011:58-65. doi:10.1109/ReCoSoC.2011.5981499
LibreCat: /record/666
DOI: 10.1109/ReCoSoC.2011.5981499

Boschmann A, Kaufmann P, Platzner M. Accurate gait phase detection using surface electromyographic signals and support vector machines. In: Proc. IEEE Int. Conf. Bioinformatics and Biomedical Technology (ICBBT). ; 2011.
LibreCat: /record/10637

Boschmann A, Platzner M, Robrecht M, Hahn M, Winkler M. Development of a pattern recognition-based myoelectric transhumeral prosthesis with multifunctional simultaneous control using a model-driven ppproach for mechatronic systems. In: Proc. MyoElectric Controls Symposium (MEC). ; 2011.
LibreCat: /record/10638

Ikonomakis N. PinSim: Schnelle Simulation Mit Pintools. Paderborn University; 2011.
LibreCat: /record/10678

Kassner H. MPI-CUDA Codegenerierung Für Nanophoton Simulationen Auf Clustern. Paderborn University; 2011.
LibreCat: /record/10680

Kaufmann P, Platzner M. Multi-objective Intrinsic Evolution of Embedded Systems. In: Müller-Schloer C, Schmeck H, Ungerer T, eds. Organic Computing---A Paradigm Shift for Complex Systems. Vol 1. Autonomic Systems. Springer Basel; 2011:193-206.
LibreCat: /record/10687

Schwabe A. Analysis of Algorithmic Approaches for Temporal Partitioning. Paderborn University; 2011.
LibreCat: /record/10736

Sekanina L, Walker JA, Kaufmann P, Plessl C, Platzner M. Evolution of Electronic Circuits. In: Cartesian Genetic Programming. Natural Computing Series. Springer Berlin Heidelberg; 2011:125-179.
LibreCat: /record/10737

Walker JA, Miller JF, Kaufmann P, Platzner M. Problem Decomposition in Cartesian Genetic Programming. In: Cartesian Genetic Programming. Natural Computing Series. Springer Berlin Heidelberg; 2011:35-99.
LibreCat: /record/10748

Welp D. User Space Scheduling for Heterogeneous Systems. Paderborn University; 2011.
LibreCat: /record/10750

Agne A, Platzner M, Lübbers E. Memory Virtualization for Multithreaded Reconfigurable Hardware. In: Proceedings of the International Conference on Field Programmable Logic and Applications (FPL). IEEE; 2011:185-188. doi:10.1109/fpl.2011.42
LibreCat: /record/13643
DOI: 10.1109/fpl.2011.42

Henkel J, Hedrich L, Herkersdorf A, et al. Design and architectures for dependable embedded systems. In: Proceedings of the Seventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis - CODES+ISSS ’11. ; 2011. doi:10.1145/2039370.2039384
LibreCat: /record/13644
DOI: 10.1145/2039370.2039384

Meyer B, Plessl C, Förstner J. Transformation of scientific algorithms to parallel computing code: subdomain support in a MPI-multi-GPU backend. In: Symp. on Application Accelerators in High Performance Computing (SAAHPC). IEEE Computer Society; 2011:60-63. doi:10.1109/SAAHPC.2011.12
LibreCat: /record/2194
DOI: 10.1109/SAAHPC.2011.12

Beisel T, Wiersema T, Plessl C, Brinkmann A. Cooperative multitasking for heterogeneous accelerators in the Linux Completely Fair Scheduler. In: Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP). IEEE Computer Society; 2011:223-226. doi:10.1109/ASAP.2011.6043273
LibreCat: /record/2193
DOI: 10.1109/ASAP.2011.6043273

Happe M, Agne A, Plessl C. Measuring and Predicting Temperature Distributions on FPGAs at Run-Time. In: Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig). IEEE; 2011:55-60. doi:10.1109/ReConFig.2011.59
LibreCat: /record/656
DOI: 10.1109/ReConFig.2011.59

Kenter T, Platzner M, Plessl C, Kauschke M. Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures. In: Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA). ACM; 2011:177-180. doi:10.1145/1950413.1950448
LibreCat: /record/2200
DOI: 10.1145/1950413.1950448

Schumacher T, Süß T, Plessl C, Platzner M. FPGA Acceleration of Communication-bound Streaming Applications: Architecture Modeling and a 3D Image Compositing Case Study. Int Journal of Recon- figurable Computing (IJRC). Published online 2011. doi:10.1155/2011/760954
LibreCat: /record/2201
DOI: 10.1155/2011/760954

Grad M, Plessl C. Just-in-time Instruction Set Extension – Feasibility and Limitations for an FPGA-based Reconfigurable ASIP Architecture. In: Proc. Reconfigurable Architectures Workshop (RAW). IEEE Computer Society; 2011:278-285. doi:10.1109/IPDPS.2011.153
LibreCat: /record/2198
DOI: 10.1109/IPDPS.2011.153

Drzevitzky S, Kastens U, Platzner M. Proof-Carrying Hardware: Concept and Prototype Tool Flow for Online Verification. International Journal of Reconfigurable Computing. 2010;2010. doi:10.1155/2010/180242
LibreCat: /record/10605
DOI: 10.1155/2010/180242

Agne A. Virtuelle Speicherverwaltung Für Hardware Threads in Rekonfigurierbaren Systemen. Paderborn University; 2010.
LibreCat: /record/10614

Boschmann A. EMG-Basierte Ganganalyse. Paderborn University; 2010.
LibreCat: /record/10629

Breitlauch D. Evolvable Cache Controller. Paderborn University; 2010.
LibreCat: /record/10642

Dridger D. Soft Microprocessors with Tightly Coupled Application-Specific Coprocessors. Paderborn University; 2010.
LibreCat: /record/10649

Graf T. Parallelization of the UCT Algorithm on HPC-Clusters. Paderborn University; 2010.
LibreCat: /record/10657

Kaufmann P, Englehart K, Platzner M. Fluctuating EMG Signals: Investigating Long-term Effects of Pattern Matching Algorithms. In: International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC). IEEE; 2010:6357-6360.
LibreCat: /record/10683

Kaufmann P, Knieper T, Platzner M. A Novel Hybrid Evolutionary Strategy and its Periodization with Multi-objective Genetic Optimizers. In: IEEE World Congress on Computational Intelligence (WCCI), Congress on Evolutionary Computation (CEC). IEEE; 2010:541-548.
LibreCat: /record/10686

Kebschull U, Platzner M, Teich J. Selected papers from the 18th International Conference on Field Programmable Logic and Applications, FPL 2008 (editorial). IET Computers Digital Techniques. 2010;4(3):157-158. doi:10.1049/iet-cdt.2010.9044
LibreCat: /record/10694
DOI: 10.1049/iet-cdt.2010.9044

Knieper T. Hybridization of Global Multi-Objective and Local Search Techniques. Paderborn University; 2010.
LibreCat: /record/10697

Knieper T, Kaufmann P, Glette K, Platzner M, Torresen J. Coping with Resource Fluctuations: The Run-time Reconfigurable Functional Unit Row Classifier Architecture. In: IEEE Intl. Conf. on Evolvable Systems (ICES). Vol 6274. LNCS. Springer; 2010:250-261.
LibreCat: /record/10699

Lübbers E, Platzner M. ReconOS: An Operating System for Dynamically Reconfigurable Hardware. In: Platzner M, Teich J, Wehn N, eds. Dynamically Reconfigurable Systems: Architectures, Design Methods and Applications. Springer-Verlag GmbH; 2010:269-290. doi:10.1007/978-90-481-3485-4_13
LibreCat: /record/10704
DOI: 10.1007/978-90-481-3485-4_13