Nofen, Barbara. Verbesserung Der Erkennungsrate Eines Systems Zur Klassifikation von EMG-Signalen Durch Den Einsatz Eines Hybriden Lagesensors. Paderborn University, 2013.
LibreCat: /record/10720

Pudelko, Daniel. Überquerung Der Styx - Betriebsparametervariation Und Fehlerverhalten Eines Platform FPGAs. Paderborn University, 2013.
LibreCat: /record/10727

Riebler, Heinrich. Identifikation Und Wiederherstellung von Kryptographischen Schlüsseln Mit FPGAs. Paderborn University, 2013.
LibreCat: /record/10730

Sprenger, Alexander. MiBenchHybridf: Erweiterung Eines Benchmarks Um Hardwarebeschleunigung. Paderborn University, 2013.
LibreCat: /record/10741

Steppeler, Philipp. Beschleunigung von Einzelbild-Erkennungsverfahren Auf Datenfluss Basierenden HPC Systemen. Paderborn University, 2013.
LibreCat: /record/10743

Toebermann, Christian, et al. “Real-Time Simulation of Distribution Grids with High Penetration of Regenerative and Distributed Generation.” Real-Time Conference, OPAL RT Paris, 2013.
LibreCat: /record/10745

Ghasemzadeh Mohammadi, Hassan, et al. “A Fast TCAD-Based Methodology for Variation Analysis of Emerging Nano-Devices.”10.1109/DFT.2013.6653587__2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS), IEEE, 2013, pp. 83–88, doi:10.1109/DFT.2013.6653587.
LibreCat: /record/10774
DOI: 10.1109/DFT.2013.6653587

Gaillardon, Pierre-Emmanuel, et al. “Vertically-Stacked Silicon Nanowire Transistors with Controllable Polarity: A Robustness Study.”10.1109/LATW.2013.6562673__2013 14th Latin American Test Workshop-LATW, IEEE, 2013, pp. 1–6, doi:10.1109/LATW.2013.6562673.
LibreCat: /record/10775
DOI: 10.1109/LATW.2013.6562673

Graf, Tobias, et al. “On Semeai Detection in Monte-Carlo Go.” Proceedings of the International Conference on Computers and Games (CG), Springer, 2013.
LibreCat: /record/13645

Riebler, Heinrich, et al. “FPGA-Accelerated Key Search for Cold-Boot Attacks against AES.”10.1109/FPT.2013.6718394__Proceedings of the International Conference on Field-Programmable Technology (FPT), IEEE, 2013, pp. 386–89, doi:10.1109/FPT.2013.6718394.
LibreCat: /record/528
DOI: 10.1109/FPT.2013.6718394

Happe, Markus, et al. “On-The-Fly Computing: A Novel Paradigm for Individualized IT Services.”10.1109/ISORC.2013.6913232__Proceedings of the 9th IEEE Workshop on Software Technology for Future Embedded and Ubiquitous Systems (SEUS), IEEE, 2013, doi:10.1109/ISORC.2013.6913232.
LibreCat: /record/505
DOI: 10.1109/ISORC.2013.6913232

Suess, Tim, et al. “Parallel Macro Pipelining on the Intel SCC Many-Core Computer.”10.1109/IPDPSW.2013.136__Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW), IEEE Computer Society, 2013, pp. 64–73, doi:10.1109/IPDPSW.2013.136.
LibreCat: /record/1787
DOI: 10.1109/IPDPSW.2013.136

Kasap, Server, and Soydan Redif. “FPGA-Based Design and Implementation of an Approximate Polynomial Matrix EVD Algorithm.”10.1109/FPT.2012.6412125__Proc. Int. Conf. on Field Programmable Technology (ICFPT), IEEE Computer Society, 2012, pp. 135–40, doi:10.1109/FPT.2012.6412125.
LibreCat: /record/2097
DOI: 10.1109/FPT.2012.6412125

Kasap, Server, and Soydan Redif. “FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm.” Int. Architecture and Engineering Symp. (ARCHENG), 2012.
LibreCat: /record/2100

Wistuba, Martin, et al. “Comparison of Bayesian Move Prediction Systems for Computer Go.”10.1109/CIG.2012.6374143__Proc. IEEE Conf. on Computational Intelligence and Games (CIG), IEEE, 2012, pp. 91–99, doi:10.1109/CIG.2012.6374143.
LibreCat: /record/2103
DOI: 10.1109/CIG.2012.6374143

Thielemans, Kris, et al. “STIR: Software for Tomographic Image Reconstruction Release 2.”10.1088/0031-9155/57/4/867__Physics in Medicine and Biology, vol. 57, no. 4, IOP Publishing, 2012, pp. 867–83, doi:10.1088/0031-9155/57/4/867.
LibreCat: /record/2172
DOI: 10.1088/0031-9155/57/4/867

Redif, Soydan, and Server Kasap. “Parallel Algorithm for Computation of Second-Order Sequential Best Rotations.”10.1080/00207217.2012.751343__Int. Journal of Electronics, vol. 100, no. 12, Taylor &; Francis, 2012, pp. 1646–51, doi:10.1080/00207217.2012.751343.
LibreCat: /record/2173
DOI: 10.1080/00207217.2012.751343

Kasap, Server, and Khaled Benkrid. “Parallel Processor Design and Implementation for Molecular Dynamics Simulations on a FPGA Parallel Computer.” Journal of Computers, vol. 7, no. 6, Academy Publishers, 2012, pp. 1312–28.
LibreCat: /record/2174

Drzevitzky, Stephanie. Proof-Carrying Hardware: A Novel Approach to Reconfigurable Hardware Security. Universität Paderborn, 2012.
LibreCat: /record/586

Plessl, Christian, et al. Programming Models for Reconfigurable Heterogeneous Multi-Cores. Awareness Magazine, 2012.
LibreCat: /record/587

Boschmann, Alexander, and Marco Platzner. “Reducing Classification Accuracy Degradation of Pattern Recognition Based Myoelectric Control Caused by Electrode Shift Using a High Density Electrode Array.” Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC), 2012.
LibreCat: /record/10636

Dridger, Denis. Design and Implementation of a Nanophotonics Simulation Personality for the Convey HC-1 Hybrid Core Computer. Paderborn University, 2012.
LibreCat: /record/10650

Giefers, Heiner. Design and Programming of Reconfigurable Mesh Based Many-Cores. Logos Verlag Berlin GmbH, 2012.
LibreCat: /record/10652

Graf, Tobias. Adaptive Playouts in Der Monte-Carlo Spielbaumsuche Am Anwendungsfall Go. Paderborn University, 2012.
LibreCat: /record/10658

Hangmann, Hendrik. Generating Adjustable Temperature Gradients on Modern FPGAs. Paderborn University, 2012.
LibreCat: /record/10667

Kaufmann, Paul, et al. “Compensating Resource Fluctuations by Means of Evolvable Hardware: The Run-Time Reconfigurable Functional Unit Row Classifier Architecture.”10.4018/jaras.2012100102__International Journal of Adaptive, Resilient and Autonomic Systems (IJARAS), vol. 3, no. 4, IGI Global, 2012, pp. 17–31, doi:10.4018/jaras.2012100102.
LibreCat: /record/10685
DOI: 10.4018/jaras.2012100102

Platzner, Marco, et al. Wieder Natürlich Gehen Und Greifen. 2012, pp. 6–11.
LibreCat: /record/10723

Schmitz, Henning. Stereo Matching on a HC-1 Hybrid Core Computer. Paderborn University, 2012.
LibreCat: /record/10734

Topmöller, Christoph. Entwicklung Eines Picoblaze Compilers Mit Dem Gentle Compiler Construction System. Paderborn University, 2012.
LibreCat: /record/10747

Wistuba, Martin. Analysis of Pattern Based Model Design and Learning in Computer-Go. Paderborn University, 2012.
LibreCat: /record/10754

Lewis, Peter, et al. An Outlook for Self-Awareness in Computing Systems. Awareness Magazine, 2012.
LibreCat: /record/13462

Meyer, Björn, et al. “Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?”10.1109/FPL.2012.6339370__Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), IEEE, 2012, pp. 189–96, doi:10.1109/FPL.2012.6339370.
LibreCat: /record/2106
DOI: 10.1109/FPL.2012.6339370

Schumacher, Tobias, et al. “IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators.”10.1016/j.micpro.2011.04.002__Microprocessors and Microsystems, vol. 36, no. 2, 2012, pp. 110–26, doi:10.1016/j.micpro.2011.04.002.
LibreCat: /record/2108
DOI: 10.1016/j.micpro.2011.04.002

Happe, Markus, et al. “Eight Ways to Put Your FPGA on Fire – A Systematic Study of Heat Generators.”10.1109/ReConFig.2012.6416745__Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), IEEE, 2012, pp. 1–8, doi:10.1109/ReConFig.2012.6416745.
LibreCat: /record/615
DOI: 10.1109/ReConFig.2012.6416745

Kenter, Tobias, et al. “Pragma Based Parallelization - Trading Hardware Efficiency for Ease of Use?”10.1109/ReConFig.2012.6416773__Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2012, pp. 1–8, doi:10.1109/ReConFig.2012.6416773.
LibreCat: /record/591
DOI: 10.1109/ReConFig.2012.6416773

Happe, Markus, et al. “Hardware/Software Platform for Self-Aware Compute Nodes.” Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS), 2012, pp. 8–9.
LibreCat: /record/609

Barrio, Pablo, et al. “Turning Control Flow Graphs into Function Calls: Code Generation for Heterogeneous Architectures.”10.1109/HPCSim.2012.6266973__Proceedings of the International Conference on High Performance Computing and Simulation (HPCS), IEEE, 2012, pp. 559–65, doi:10.1109/HPCSim.2012.6266973.
LibreCat: /record/567
DOI: 10.1109/HPCSim.2012.6266973

Rüthing, Christoph, et al. “Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs.”10.1109/FPL.2012.6339370__Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), IEEE, 2012, pp. 559–62, doi:10.1109/FPL.2012.6339370.
LibreCat: /record/612
DOI: 10.1109/FPL.2012.6339370

Beisel, Tobias, et al. “Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux.” Proc. Workshop on Computer Architecture and Operating System Co-Design (CAOS), 2012.
LibreCat: /record/2180

Grad, Mariusz, and Christian Plessl. “On the Feasibility and Limitations of Just-In-Time Instruction Set Extension for FPGA-Based Reconfigurable Processors.”10.1155/2012/418315__Int. Journal of Reconfigurable Computing (IJRC), Hindawi Publishing Corp., 2012, doi:10.1155/2012/418315.
LibreCat: /record/2177
DOI: 10.1155/2012/418315

Kenter, Tobias, et al. “Estimation and Partitioning for CPU-Accelerator Architectures.” Intel European Research and Innovation Conference, 2011.
LibreCat: /record/2191

Plessl, Christian, and Marco Platzner. “Hardware Virtualization on Dynamically Reconfigurable Embedded Processors.”10.4018/978-1-60960-086-0__Reconfigurable Embedded Control Systems: Applications for Flexibility and Agility, edited by Mohamed Khalgui and Hans-Michael Hanisch, IGI Global, 2011, doi:10.4018/978-1-60960-086-0.
LibreCat: /record/2202
DOI: 10.4018/978-1-60960-086-0

Graf, Tobias, et al. “Parallel Monte-Carlo Tree Search for HPC Systems.”10.1007/978-3-642-23397-5_36__Proc. European Conf. on Parallel Processing (Euro-Par), vol. 6853, Springer, 2011, doi:10.1007/978-3-642-23397-5_36.
LibreCat: /record/2204
DOI: 10.1007/978-3-642-23397-5_36

Drzevitzky, Stephanie, and Marco Platzner. “Achieving Hardware Security for Reconû01gurable Systems on Chip by a Proof-Carrying Code Approach.”10.1109/ReCoSoC.2011.5981499__Proceedings of the 6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC), 2011, pp. 58–65, doi:10.1109/ReCoSoC.2011.5981499.
LibreCat: /record/666
DOI: 10.1109/ReCoSoC.2011.5981499

Boschmann, Alexander, et al. “Accurate Gait Phase Detection Using Surface Electromyographic Signals and Support Vector Machines.” Proc. IEEE Int. Conf. Bioinformatics and Biomedical Technology (ICBBT), 2011.
LibreCat: /record/10637

Boschmann, Alexander, et al. “Development of a Pattern Recognition-Based Myoelectric Transhumeral Prosthesis with Multifunctional Simultaneous Control Using a Model-Driven Ppproach for Mechatronic Systems.” Proc. MyoElectric Controls Symposium (MEC), 2011.
LibreCat: /record/10638

Ikonomakis, Nikolaos. PinSim: Schnelle Simulation Mit Pintools. Paderborn University, 2011.
LibreCat: /record/10678

Kassner, Hendrik. MPI-CUDA Codegenerierung Für Nanophoton Simulationen Auf Clustern. Paderborn University, 2011.
LibreCat: /record/10680

Kaufmann, Paul, and Marco Platzner. “Multi-Objective Intrinsic Evolution of Embedded Systems.” Organic Computing---A Paradigm Shift for Complex Systems, edited by Christian Müller-Schloer et al., vol. 1, Springer Basel, 2011, pp. 193–206.
LibreCat: /record/10687

Schwabe, Arne. Analysis of Algorithmic Approaches for Temporal Partitioning. Paderborn University, 2011.
LibreCat: /record/10736

Sekanina, Lukas, et al. “Evolution of Electronic Circuits.” Cartesian Genetic Programming, Springer Berlin Heidelberg, 2011, pp. 125–79.
LibreCat: /record/10737

Walker, James Alfred, et al. “Problem Decomposition in Cartesian Genetic Programming.” Cartesian Genetic Programming, Springer Berlin Heidelberg, 2011, pp. 35–99.
LibreCat: /record/10748

Welp, Daniel. User Space Scheduling for Heterogeneous Systems. Paderborn University, 2011.
LibreCat: /record/10750

Agne, Andreas, et al. “Memory Virtualization for Multithreaded Reconfigurable Hardware.”10.1109/fpl.2011.42__Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), IEEE, 2011, pp. 185–88, doi:10.1109/fpl.2011.42.
LibreCat: /record/13643
DOI: 10.1109/fpl.2011.42

Henkel, Jörg, et al. “Design and Architectures for Dependable Embedded Systems.”10.1145/2039370.2039384__Proceedings of the Seventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis - CODES+ISSS ’11, 2011, doi:10.1145/2039370.2039384.
LibreCat: /record/13644
DOI: 10.1145/2039370.2039384

Meyer, Björn, et al. “Transformation of Scientific Algorithms to Parallel Computing Code: Subdomain Support in a MPI-Multi-GPU Backend.”10.1109/SAAHPC.2011.12__Symp. on Application Accelerators in High Performance Computing (SAAHPC), IEEE Computer Society, 2011, pp. 60–63, doi:10.1109/SAAHPC.2011.12.
LibreCat: /record/2194
DOI: 10.1109/SAAHPC.2011.12

Beisel, Tobias, et al. “Cooperative Multitasking for Heterogeneous Accelerators in the Linux Completely Fair Scheduler.”10.1109/ASAP.2011.6043273__Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), IEEE Computer Society, 2011, pp. 223–26, doi:10.1109/ASAP.2011.6043273.
LibreCat: /record/2193
DOI: 10.1109/ASAP.2011.6043273

Happe, Markus, et al. “Measuring and Predicting Temperature Distributions on FPGAs at Run-Time.”10.1109/ReConFig.2011.59__Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig), IEEE, 2011, pp. 55–60, doi:10.1109/ReConFig.2011.59.
LibreCat: /record/656
DOI: 10.1109/ReConFig.2011.59

Kenter, Tobias, et al. “Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures.”10.1145/1950413.1950448__Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA), ACM, 2011, pp. 177–80, doi:10.1145/1950413.1950448.
LibreCat: /record/2200
DOI: 10.1145/1950413.1950448

Schumacher, Tobias, et al. “FPGA Acceleration of Communication-Bound Streaming Applications: Architecture Modeling and a 3D Image Compositing Case Study.”10.1155/2011/760954__Int. Journal of Recon- Figurable Computing (IJRC), Hindawi Publishing Corp., 2011, doi:10.1155/2011/760954.
LibreCat: /record/2201
DOI: 10.1155/2011/760954

Grad, Mariusz, and Christian Plessl. “Just-in-Time Instruction Set Extension – Feasibility and Limitations for an FPGA-Based Reconfigurable ASIP Architecture.”10.1109/IPDPS.2011.153__Proc. Reconfigurable Architectures Workshop (RAW), IEEE Computer Society, 2011, pp. 278–85, doi:10.1109/IPDPS.2011.153.
LibreCat: /record/2198
DOI: 10.1109/IPDPS.2011.153

Drzevitzky, Stephanie, et al. “Proof-Carrying Hardware: Concept and Prototype Tool Flow for Online Verification.”10.1155/2010/180242__International Journal of Reconfigurable Computing, vol. 2010, Hindawi Publishing Corporation, 2010, doi:10.1155/2010/180242.
LibreCat: /record/10605
DOI: 10.1155/2010/180242

Agne, Andreas. Virtuelle Speicherverwaltung Für Hardware Threads in Rekonfigurierbaren Systemen. Paderborn University, 2010.
LibreCat: /record/10614

Boschmann, Alexander. EMG-Basierte Ganganalyse. Paderborn University, 2010.
LibreCat: /record/10629

Breitlauch, Daniel. Evolvable Cache Controller. Paderborn University, 2010.
LibreCat: /record/10642

Dridger, Denis. Soft Microprocessors with Tightly Coupled Application-Specific Coprocessors. Paderborn University, 2010.
LibreCat: /record/10649

Graf, Tobias. Parallelization of the UCT Algorithm on HPC-Clusters. Paderborn University, 2010.
LibreCat: /record/10657

Kaufmann, Paul, et al. “Fluctuating EMG Signals: Investigating Long-Term Effects of Pattern Matching Algorithms.” International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC), IEEE, 2010, pp. 6357–60.
LibreCat: /record/10683

Kaufmann, Paul, et al. “A Novel Hybrid Evolutionary Strategy and Its Periodization with Multi-Objective Genetic Optimizers.” IEEE World Congress on Computational Intelligence (WCCI), Congress on Evolutionary Computation (CEC), IEEE, 2010, pp. 541–48.
LibreCat: /record/10686

Kebschull, Udo, et al. “Selected Papers from the 18th International Conference on Field Programmable Logic and Applications, FPL 2008 (Editorial).”10.1049/iet-cdt.2010.9044__IET Computers Digital Techniques, vol. 4, no. 3, 2010, pp. 157–58, doi:10.1049/iet-cdt.2010.9044.
LibreCat: /record/10694
DOI: 10.1049/iet-cdt.2010.9044

Knieper, Tobias. Hybridization of Global Multi-Objective and Local Search Techniques. Paderborn University, 2010.
LibreCat: /record/10697

Knieper, Tobias, et al. “Coping with Resource Fluctuations: The Run-Time Reconfigurable Functional Unit Row Classifier Architecture.” IEEE Intl. Conf. on Evolvable Systems (ICES), vol. 6274, Springer, 2010, pp. 250–61.
LibreCat: /record/10699

Lübbers, Enno, and Marco Platzner. “ReconOS: An Operating System for Dynamically Reconfigurable Hardware.”10.1007/978-90-481-3485-4_13__Dynamically Reconfigurable Systems: Architectures, Design Methods and Applications, edited by Marco Platzner et al., Springer-Verlag GmbH, 2010, pp. 269–90, doi:10.1007/978-90-481-3485-4_13.
LibreCat: /record/10704
DOI: 10.1007/978-90-481-3485-4_13

Meiche, Robert. FPGA/CPU Multicore-Plattform Für ReconOS/ECos. Paderborn University, 2010.
LibreCat: /record/10710

Niekamp, Manuel. Transparente Hardwarebeschleunigung Durch Shared Library Interposing. Paderborn University, 2010.
LibreCat: /record/10717

Runde, Bodo. A Token-Ring Network-On-Chip for Message Passing in ReconOS. Paderborn University, 2010.
LibreCat: /record/10731

Wiersema, Tobias. Scheduling Support for Heterogeneous Hardware Accelerators under Linux. Paderborn University, 2010.
LibreCat: /record/10752

Platzner, Marco, et al., editors. Dynamically Reconfigurable Systems: Architectures, Design Methods and Applications. Springer-Verlag GmbH, 2010, doi:10.1007/978-90-481-3485-4.
LibreCat: /record/10763
DOI: 10.1007/978-90-481-3485-4

Khatir, Mehrdad, et al. “Sub-Threshold Charge Recovery Circuits.”10.1109/ICCD.2010.5647815__Computer Design (ICCD), 2010 IEEE International Conference On, IEEE, 2010, pp. 138–44, doi:10.1109/ICCD.2010.5647815.
LibreCat: /record/10776
DOI: 10.1109/ICCD.2010.5647815

Giefers, Heiner, and Marco Platzner. “A Triple Hybrid Interconnect for Many-Cores: Reconfigurable Mesh, NoC and Barrier.” Proceedings of the 20th International Conference on Field Programmable Logic and Applications (FPL), IEEE, 2010.
LibreCat: /record/13640

Schäfer, Wilhelm, et al. “Engineering Self-Coordinating Software Intensive Systems.” Proceedings of the Foundations of Software Engineering (FSE) and NITR &; D/SPD Working Conference on the Future of Software Engineering Research (FoSER), 2010, pp. 321–24.
LibreCat: /record/13641

Giefers, Heiner, and Marco Platzner. “A Self-Reconfigurable Lightweight Interconnect for Scalable Processor Fabrics.” Proceedings of the 10th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2010.
LibreCat: /record/13642

Lübbers, Enno, et al. “Towards Adaptive Networking for Embedded Devices Based on Reconfigurable Hardware.” Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2010, pp. 225–31.
LibreCat: /record/2223

Grad, Mariusz, and Christian Plessl. “Pruning the Design Space for Just-In-Time Processor Customization.”10.1109/ReConFig.2010.19__Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), IEEE Computer Society, 2010, pp. 67–72, doi:10.1109/ReConFig.2010.19.
LibreCat: /record/2216
DOI: 10.1109/ReConFig.2010.19

Grad, Mariusz, and Christian Plessl. “An Open Source Circuit Library with Benchmarking Facilities.” Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2010, pp. 144–50.
LibreCat: /record/2224

Andrews, David, and Christian Plessl. “Configurable Processor Architectures: History and Trends.” Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2010, p. 165.
LibreCat: /record/2220

Plaks, Toomas P., et al., editors. Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press, 2010.
LibreCat: /record/2222

Beisel, Tobias, et al. “Using Shared Library Interposing for Transparent Acceleration in Systems with Heterogeneous Hardware Accelerators.”10.1109/ASAP.2010.5540798__Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), IEEE Computer Society, 2010, pp. 65–72, doi:10.1109/ASAP.2010.5540798.
LibreCat: /record/2226
DOI: 10.1109/ASAP.2010.5540798

Keller, Ariane, et al. “Reconfigurable Nodes for Future Networks.”10.1109/GLOCOMW.2010.5700341__Proc. IEEE Globecom Workshop on Network of the Future (FutureNet), IEEE, 2010, pp. 372–76, doi:10.1109/GLOCOMW.2010.5700341.
LibreCat: /record/2206
DOI: 10.1109/GLOCOMW.2010.5700341

Kenter, Tobias, et al. “Performance Estimation for the Exploration of CPU-Accelerator Architectures.” Proc. Workshop on Architectural Research Prototyping (WARP), International Symposium on Computer Architecture (ISCA), edited by Omar Hammami and Sandra Larrabee, 2010.
LibreCat: /record/2228

Boschmann, Alexander, et al. “Towards Multi-Movement Hand Prostheses: Combining Adaptive Classification with High Precision Sockets.” Proc. Technically Assisted Rehabilitation (TAR), 2009.
LibreCat: /record/10639

Kostin, Alexander. Evolvable Robot Controller. Paderborn University, 2009.
LibreCat: /record/10702

Lübbers, Enno, and Marco Platzner. “ReconOS: Multithreaded Programming for Reconfigurable Computers.”10.1145/1596532.1596540__ACM Transactions on Embedded Computing Systems, vol. 9, no. 1, 2009, pp. 8:1-8:33, doi:10.1145/1596532.1596540.
LibreCat: /record/10703
DOI: 10.1145/1596532.1596540

Tofall, Martin. Compiler for a Custom Instruction Set CPU. Paderborn University, 2009.
LibreCat: /record/10746

Warkentin, Alexander. Coarse-Grained CGP Model Using Xilinx Virte DSE Functional Units. Paderborn University, 2009.
LibreCat: /record/10749

Wildenhain, Benedikt. Implementierung von Kryptographie-Hardwarebeschleunigern Für Das HW/SW-Betriebssystem ReconOS. Paderborn University, 2009.
LibreCat: /record/10753

Ghasemzadeh Mohammadi, Hassan, et al. “Signature Self Checking (SSC): A Low-Cost Reliable Control Logic for Pipelined Microprocessors.”10.1109/PRDC.2009.69__Dependable Computing (PRDC), 2009 IEEE Pacific Rim International Symposium On, IEEE, 2009, pp. 252–55, doi:10.1109/PRDC.2009.69.
LibreCat: /record/10777
DOI: 10.1109/PRDC.2009.69

Happe, Markus, et al. “A Multithreaded Framework for Sequential Monte Carlo Methods on CPU/FPGA Platforms.” Proceedings of the International Workshop on Applied Reconfigurable Computing (ARC), Springer, 2009.
LibreCat: /record/13632

Giefers, Heiner, and Marco Platzner. “Towards Models for Many-Cores: The Case for the Reconfigurable Mesh.” Proceedings of the Workshop on Many-Cores, International Conference on Architecture of Computing Systems (ARCS), 2009.
LibreCat: /record/13634

Giefers, Heiner, and Marco Platzner. “ARMLang: A Language and Compiler for Programming Reconfigurable Mesh Many-Cores.” Reconfigurable Architectures Workshop (RAW), Proceedings of the International Parallel and Distributed Processing Symposium, IEEE, 2009.
LibreCat: /record/13635