Lübbers, E., &; Platzner, M. (2009). Cooperative Multithreading in Dynamically Reconfigurable Systems. In Proceedings of the 19th International Workshop on Field Programmable Logic and Applications (FPL) . IEEE.
LibreCat: /record/13636

Giefers, H., &; Platzner, M. (2009). Program-driven Fine-grained Power Management for the Reconfigurable Mesh. In Proceedings of the 19th International Workshop on Field Programmable Logic and Applications (FPL) . IEEE.
LibreCat: /record/13637

Happe, M., Lübbers, E., &; Platzner, M. (2009). An adaptive Sequential Monte Carlo framework with runtime HW/SW repartitioning. In Proceedings of the 2009 International Conference on Field-Programmable Technology (FPT). IEEE.https://doi.org/10.1109/fpt.2009.5377645 
LibreCat: /record/13638
DOI: 10.1109/fpt.2009.5377645

Drzevitzky, S., Kastens, U., &; Platzner, M. (2009). Proof-carrying Hardware: Towards Runtime Verification of Reconfigurable Modules. In Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE.
LibreCat: /record/13639

Schumacher, T., Plessl, C., &; Platzner, M. (2009). IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing. Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), 275–278.https://doi.org/10.1109/FCCM.2009.25 
LibreCat: /record/2350
DOI: 10.1109/FCCM.2009.25

Kaufmann, P., Plessl, C., &; Platzner, M. (2009). EvoCaches: Application-specific Adaptation of Cache Mapping. Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS), 11–18.
LibreCat: /record/2262

Schumacher, T., Süß, T., Plessl, C., &; Platzner, M. (2009). Communication Performance Characterization for Reconfigurable Accelerator Design on the . Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), 119–124.https://doi.org/10.1109/ReConFig.2009.32 
LibreCat: /record/2238
DOI: 10.1109/ReConFig.2009.32

Schumacher, T., Plessl, C., &; Platzner, M. (2009). An Accelerator for k-th Nearest Neighbor Thinning Based on the IMORC Infrastructure. Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), 338–344.
LibreCat: /record/2261

Grad, M., &; Plessl, C. (2009). Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX. Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 319–322.
LibreCat: /record/2263

Beisel, T., Lietsch, S., &; Thielemans, K. (2008). A method for OSEM PET reconstruction on parallel architectures using STIR. In IEEE Nuclear Science Symposium Conference Record (NSS) (pp. 4161–4168). IEEE.https://doi.org/10.1109/NSSMIC.2008.4774198 
LibreCat: /record/2358
DOI: 10.1109/NSSMIC.2008.4774198

Platzner, M., Döhre, S., Happe, M., Kenter, T., Lorenz, U., Schumacher, T.,  Warkentin, A. (2008). The GOmputer: Accelerating GO with FPGAs. In Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) (pp. 245–251). CSREA Press.
LibreCat: /record/2365

Boschmann, A. (2008). Aufbau und experimentelle Bewertung eines Systems zur Langzeitklassiû01kation von EMG-Signalen. Paderborn University.
LibreCat: /record/10628

Breitlauch, D. (2008). Selbstoptimierender Cache-Kontroller. Paderborn University.
LibreCat: /record/10641

Ceylan, T., &; Yalcin, C. (2008). Verteilte Simulation von mobilen Robotern mit EyeSim. Paderborn University.
LibreCat: /record/10644

Glette, K., Gruber, T., Kaufmann, P., Torresen, J., Sick, B., &; Platzner, M. (2008). Comparing Evolvable Hardware to Conventional Classifiers for Electromyographic Prosthetic Hand Control. In IEEE Adaptive Hardware and Systems (AHS) (pp. 32–39). IEEE.
LibreCat: /record/10653

Glette, K., Torresen, J., Kaufmann, P., &; Platzner, M. (2008). A Comparison of Evolvable Hardware Architectures for Classification Tasks. In IEEE Intl. Conf. on Evolvable Systems (ICES) (Vol. 5216, pp. 22–33). Springer.
LibreCat: /record/10656

Happe, M. (2008). Parallelisierung und Hardware- / Software - Codesign von Partikelfiltern. Paderborn University.
LibreCat: /record/10669

Torresen, J., Glette, K., Platzner, M., &; Kaufmann, P. (2008). Evolvable Hardware - Tutorial at Architecture of Computing Systems (ARCS).
LibreCat: /record/10690

Kaufmann, P., &; Platzner, M. (2008). Advanced Techniques for the Creation and Propagation of Modules in Cartesian Genetic Programming. In Genetic and Evolutionary Computation (GECCO) (pp. 1219–1226). ACM Press.
LibreCat: /record/10691

Knieper, T. (2008). Implementierung und Bewertung des multikriteriellen Optimierungsverfahrens IBEA für den automatisierten Schaltungsentwurf. Paderborn University.
LibreCat: /record/10696

Knieper, T., Defo, B., Kaufmann, P., &; Platzner, M. (2008). On Robust Evolution of Digital Hardware. In Biologically Inspired Collaborative Computing (BICC) (Vol. 268, pp. 2313–222). Springer.
LibreCat: /record/10698

Niklas, J. (2008). Eine Monitoring- und Debugging-Infrastruktur für hybride HW/SW-Systeme. Paderborn University.
LibreCat: /record/10718

Östermann, M. (2008). Raytracing on a Custom Instruction Set CPU. Paderborn University.
LibreCat: /record/10721

Westerheide, N. (2008). Design and Evaluation of MicroBlaze Multi-core Architectures. Paderborn University.
LibreCat: /record/10751

Ghasemzadeh Mohammadi, H., Tabkhi, H., Miremadi, S. G., &; Ejlali, A. (2008). A cost-effective error detection and roll-back recovery technique for embedded microprocessor control logic. In 2008 International Conference on Microelectronics (pp. 444–447). IEEE.https://doi.org/10.1109/ICM.2008.5393497 
LibreCat: /record/10778
DOI: 10.1109/ICM.2008.5393497

Giefers, H., &; Platzner, M. (2008). Realizing Reconfigurable Mesh Algorithms on Softcore Arrays. In Proceedings of the International Symposium on Systems, Architectures, Modeling and Simulation (SAMOS). IEEE.
LibreCat: /record/13629

Lübbers, E., &; Platzner, M. (2008). Communication and Synchronization in Multithreaded Reconfigurable Computing Systems. In Proceedings of the 8th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press.
LibreCat: /record/13630

Lübbers, E., &; Platzner, M. (2008). A portable abstraction layer for hardware threads. In Proceedings of the 18th International Conference on Field Programmable Logic and Applications (FPL). IEEE.https://doi.org/10.1109/fpl.2008.4629901 
LibreCat: /record/13631
DOI: 10.1109/fpl.2008.4629901

Schumacher, T., Meiche, R., Kaufmann, P., Lübbers, E., Plessl, C., &; Platzner, M. (2008). A Hardware Accelerator for k-th Nearest Neighbor Thinning. Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 245–251.
LibreCat: /record/2364

Schumacher, T., Plessl, C., &; Platzner, M. (2008). IMORC: An infrastructure for performance monitoring and optimization of reconfigurable computers. Many-Core and Reconfigurable Supercomputing Conference (MRSC).
LibreCat: /record/2372

Kaufmann, P., &; Platzner, M. (2007). MOVES: A Modular Framework for Hardware Evolution. In Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007) (pp. 447–454). Edinburgh, UK: IEEE.https://doi.org/10.1109/ahs.2007.73 
LibreCat: /record/6508
DOI: 10.1109/ahs.2007.73

Beisel, T. (2007). Entwurf und Evaluation eines parallelen Verfahrens zur Bildrekonstruktion in der Positronen-Emissions-Tomographie auf Multi-Core-Architekturen. Paderborn University.
LibreCat: /record/10623

Bergmann, N., Platzner, M., &; Teich, J. (2007). Dynamically Reconfigurable Architectures (editorial). EURASIP Journal on Embedded Systems, 2007, 1–2.https://doi.org/10.1155/2007/28405 
LibreCat: /record/10625
DOI: 10.1155/2007/28405

Ceylan, T., &; Yalcin, C. (2007). Distributed Simulation of mobile Robots using EyeSim. Paderborn University.
LibreCat: /record/10643

Danne, K., Mühlenbernd, R., &; Platzner, M. (2007). Server-based execution of periodic tasks on dynamically reconfigurable hardware. IET Computers Digital Techniques, 1(4), 295–302.https://doi.org/10.1049/iet-cdt:20060186 
LibreCat: /record/10646
DOI: 10.1049/iet-cdt:20060186

Defo, B. (2007). A Comparison of Multi-Objective Evolutionary Algorithms for Automated Circuit Design and Optimization. Paderborn University.
LibreCat: /record/10647

Döhre, S. (2007). Entwurf und Implementierung einer RocketIO-basierten Kommunikationsschnittstelle für Multi-FPGA Systeme. Paderborn University.
LibreCat: /record/10648

Kaufmann, P., &; Platzner, M. (2007). Toward Self-adaptive Embedded Systems: Multi-objective Hardware Evolution. In Architecture of Computing Systems (ARCS) (Vol. 4415, pp. 199–208). Springer.
LibreCat: /record/10689

Meiche, R. (2007). VHDL-Implementierung eines Clustering-Verfahrens für multikriterielle Optimierungsalgorithmen. Paderborn University.
LibreCat: /record/10709

Reisch, W. (2007). Bildverarbeitungs-Architekturen und -Bibliotheken für das rekonfigurierbare Betriebssystem ReconOS. Paderborn University.
LibreCat: /record/10728

Rethmeier, E. (2007). Konzeption und Implementierung einer Microsoft Windows CE 5.0 Plattform für ein ARM-basiertes eingebettetes Rechnersystem. Paderborn University.
LibreCat: /record/10729

Schumacher, T., Lübbers, E., Kaufmann, P., &; Platzner, M. (2007). Accelerating the Cube Cut Problem with an FPGA-Augmented Compute Cluster. In Proceedings of the ParaFPGA Symposium, International Conference on Parallel Computing: Architectures, Algorithms and Applications (PARCO) (Vol. 15, pp. 749–756). IOS Press.
LibreCat: /record/10735

Giefers, H., &; Platzner, M. (2007). A Many-Core Implementation Based on the Reconfigurable Mesh Model. In Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL). IEEE.https://doi.org/10.1109/fpl.2007.4380623 
LibreCat: /record/13627
DOI: 10.1109/fpl.2007.4380623

Lübbers, E., &; Platzner, M. (2007). ReconOS: An RTOS Supporting Hard-and Software Threads. In Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL). IEEE.https://doi.org/10.1109/fpl.2007.4380686 
LibreCat: /record/13628
DOI: 10.1109/fpl.2007.4380686

Plessl, C., Platzner, M., &; Thiele, L. (2006). Optimal Temporal Partitioning based on Slowdown and Retiming. In Proc. Int. Conf. on Field Programmable Technology (ICFPT) (pp. 345–348). IEEE Computer Society.https://doi.org/10.1109/FPT.2006.270344 
LibreCat: /record/2401
DOI: 10.1109/FPT.2006.270344

Kaufmann, P., &; Platzner, M. (2006). Multi-objective Intrinsic Hardware Evolution. In Intl. Conf. Military Applications of Programmable Logic Devices (MAPLD).
LibreCat: /record/10688

Mühlenbernd, R. (2006). FPGA-Implementierung eines server-basierten Schedulers für periodische Hardwaretasks. Paderborn University.
LibreCat: /record/10716

Danne, K., Mühlenbernd, R., &; Platzner, M. (2006). Executing Hardware Tasks on Dynamically Reconfigurable Devices under Real-time Conditions. In Proceedings of the 16th International Conference on Field Programmable Logic and Applications (FPL). IEEE.
LibreCat: /record/13624

Danne, K., &; Platzner, M. (2006). An EDF Schedulability Test for Periodic Tasks on Reconfigurable Hardware Devices. In In ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES).
LibreCat: /record/13625

Danne, K., &; Platzner, M. (2006). Partitioned Scheduling of Periodic Real-time Tasks onto Reconfigurable Hardware. In Proceedings of the 13th Reconfigurable Architectures Workshop (RAW). IEEE CS Press.
LibreCat: /record/13626

Plessl, C., &; Platzner, M. (2005). Zippy – A coarse-grained reconfigurable array with support for hardware virtualization. In Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP) (pp. 213–218). IEEE Computer Society.https://doi.org/10.1109/ASAP.2005.69 
LibreCat: /record/2411
DOI: 10.1109/ASAP.2005.69

Enzler, R., Plessl, C., &; Platzner, M. (2005). System-level performance evaluation of reconfigurable processors. Microprocessors and Microsystems, 29(2–3), 63–73.https://doi.org/10.1016/j.micpro.2004.06.004 
LibreCat: /record/2412
DOI: 10.1016/j.micpro.2004.06.004

Danne, K., &; Platzner, M. (2005). Periodic real-time scheduling for FPGA computers. In Proceedings of the Third International Workshop on Intelligent Solutions in Embedded Systems (WISES).https://doi.org/10.1109/wises.2005.1438720 
LibreCat: /record/13621
DOI: 10.1109/wises.2005.1438720

Danne, K., &; Platzner, M. (2005). Memory-demanding Periodic Real-time Applications on FPGA Computers. In Work-in-Progress Proceedings of the 17th Euromicro Conference on Real-time Systems (ECRTS).
LibreCat: /record/13622

Danne, K., &; Platzner, M. (2005). A heuristic approach to schedule periodic real-time tasks on reconfigurable hardware. In Proceedings of the 15th International Conference on Field Programmable Logic and Applications (FPL). IEEE CS Press.https://doi.org/10.1109/fpl.2005.1515787 
LibreCat: /record/13623
DOI: 10.1109/fpl.2005.1515787

Plessl, C., &; Platzner, M. (2004). Virtualization of Hardware – Introduction and Survey. In Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) (pp. 63–69). CSREA Press.
LibreCat: /record/2415

Steiger, C., Walder, H., &; Platzner, M. (2004). Operating systems for reconfigurable embedded platforms: online scheduling of real-time tasks. IEEE Transactions on Computers, 53(11), 1393–1407.https://doi.org/10.1109/tc.2004.99 
LibreCat: /record/10742
DOI: 10.1109/tc.2004.99

Walder, H., &; Platzner, M. (2004). A Runtime Environment for Reconfigurable Hardware Operating Systems. In Proceedings of the 14th International Conference on Field Programmable Logic and Applications (FPL) (pp. 831–835). Berlin, Heidelberg: Springer.https://doi.org/10.1007/978-3-540-30117-2_84 
LibreCat: /record/13618
DOI: 10.1007/978-3-540-30117-2_84

Walder, H., Nobs, S., &; Platzner, M. (2004). XF-BOARD: A Prototyping Platform for Reconfigurable Hardware Operating Systems. In Proceedings of the 4th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press.
LibreCat: /record/13619

Dyer, M., Platzner, M., &; Thiele, L. (2004). Efficient Execution of Process Networks on a Reconfigurable Hardware Virtual Machine. In Proceedings 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM). IEEE CS Press.https://doi.org/10.1109/fccm.2004.31 
LibreCat: /record/13620
DOI: 10.1109/fccm.2004.31

Plessl, C., &; Platzner, M. (2003). TKDM – A Reconfigurable Co-processor in a PC’s Memory Slot. In Proc. Int. Conf. on Field Programmable Technology (ICFPT) (pp. 252–259). IEEE Computer Society.https://doi.org/10.1109/FPT.2003.1275755 
LibreCat: /record/2418
DOI: 10.1109/FPT.2003.1275755

Plessl, C., Enzler, R., Walder, H., Beutel, J., Platzner, M., Thiele, L., &; Tröster, G. (2003). The Case for Reconfigurable Hardware in Wearable Computing. Personal and Ubiquitous Computing, 7(5), 299–308.https://doi.org/10.1007/s00779-003-0243-x 
LibreCat: /record/2419
DOI: 10.1007/s00779-003-0243-x

Plessl, C., &; Platzner, M. (2003). Instance-Specific Accelerators for Minimum Covering. Journal of Supercomputing, 26(2), 109–129.https://doi.org/10.1023/a:1024443416592 
LibreCat: /record/2420
DOI: 10.1023/a:1024443416592

Enzler, R., Plessl, C., &; Platzner, M. (2003). Virtualizing Hardware with Multi-Context Reconfigurable Arrays. In Proc. Int. Conf. on Field Programmable Logic and Applications (FPL) (Vol. 2778, pp. 151–160). Springer.https://doi.org/10.1007/b12007 
LibreCat: /record/2421
DOI: 10.1007/b12007

Enzler, R., Plessl, C., &; Platzner, M. (2003). Co-simulation of a Hybrid Multi-Context Architecture. In Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) (pp. 174–180). CSREA Press.
LibreCat: /record/2422

Walder, H., &; Platzner, M. (2003). Online scheduling for block-partitioned reconfigurable devices. In Proceedings Design, Automation and Test in Europe Conference (DATE) (pp. 290–295). IEEE CS Press.https://doi.org/10.1109/date.2003.1253622 
LibreCat: /record/13612
DOI: 10.1109/date.2003.1253622

Walder, H., Steiger, C., &; Platzner, M. (2003). Fast online task placement on FPGAs: free space partitioning and 2D-hashing. In Proceedings International Parallel and Distributed Processing Symposium. IEEE CS Press.https://doi.org/10.1109/ipdps.2003.1213329 
LibreCat: /record/13613
DOI: 10.1109/ipdps.2003.1213329

Walder, H., &; Platzner, M. (2003). Reconfigurable Hardware Operating Systems: From Design Concepts to Realizations. In Proceedings of the 3rd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA) (pp. 284–287). CSREA Press.
LibreCat: /record/13614

Steiger, C., Walder, H., &; Platzner, M. (2003). Heuristics for Online Scheduling Real-Time Tasks to Partially Reconfigurable Devices. In Proceedings of the 13th International Conference on Field Programmable Logic and Applications (FPL) (pp. 575–584). Berlin, Heidelberg: Springer.https://doi.org/10.1007/978-3-540-45234-8_56 
LibreCat: /record/13615
DOI: 10.1007/978-3-540-45234-8_56

Steiger, C., Walder, H., Platzner, M., &; Thiele, L. (2003). Online scheduling and placement of real-time tasks to partially reconfigurable devices. In Proceedings 24th IEEE International Real-Time Systems Symposium (RTSS) (pp. 252–235). IEEE CS Press.https://doi.org/10.1109/real.2003.1253269 
LibreCat: /record/13617
DOI: 10.1109/real.2003.1253269

Plessl, C., Enzler, R., Walder, H., Beutel, J., Platzner, M., &; Thiele, L. (2002). Reconfigurable Hardware in Wearable Computing Nodes. In Proc. Int. Symp. on Wearable Computers (ISWC) (pp. 215–222). IEEE Computer Society.https://doi.org/10.1109/ISWC.2002.1167250 
LibreCat: /record/2423
DOI: 10.1109/ISWC.2002.1167250

Dyer, M., Plessl, C., &; Platzner, M. (2002). Partially Reconfigurable Cores for Xilinx Virtex. In Proc. Int. Conf. on Field Programmable Logic and Applications (FPL) (Vol. 2438, pp. 292–301). Springer.https://doi.org/10.1007/3-540-46117-5 
LibreCat: /record/2424
DOI: 10.1007/3-540-46117-5

Plessl, C., &; Platzner, M. (2002). Custom Computing Machines for the Set Covering Problem. In Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM) (pp. 163–172). IEEE Computer Society.https://doi.org/10.1109/FPGA.2002.1106671 
LibreCat: /record/2425
DOI: 10.1109/FPGA.2002.1106671

Eisenring, M., &; Platzner, M. (2002). A Framework for Run-time Reconfigurable Systems. The Journal of Supercomputing, 21(2), 145–159.https://doi.org/10.1023/a:1013627403946 
LibreCat: /record/10651
DOI: 10.1023/a:1013627403946

Walder, H., &; Platzner, M. (2002). Non-preemptive Multitasking on FPGAs: Task Placement and Footprint Transform. In Proceedings of the 2nd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA) (pp. 24–30). CSREA Press.
LibreCat: /record/13611

Plessl, C., &; Platzner, M. (2001). Instance-Specific Accelerators for Minimum Covering. In Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) (pp. 85–91). CSREA Press.
LibreCat: /record/2428

Enzler, R., Platzner, M., Plessl, C., Thiele, L., &; Tröster, G. (2001). Reconfigurable Processors for Handhelds and Wearables: Application Analysis. In Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III (Vol. 4525, pp. 135–146).https://doi.org/10.1117/12.434376 
LibreCat: /record/2432
DOI: 10.1117/12.434376

Mencer, O., Platzner, M., Morf, M., &; J. Flynn, M. (2001). Object-oriented domain specific compilers for programming FPGAs. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 9(1), 205–210.https://doi.org/10.1109/92.920835 
LibreCat: /record/10713
DOI: 10.1109/92.920835

Enzler, R., &; Platzner, M. (2001). Dynamically Reconfigurable Processors. TELEMATIK, Zeitschrift des Telematik-Ingebieur-Verbandes 7(1).
LibreCat: /record/13463

Platzner, M. (2000). Reconfigurable accelerators for combinatorial problems. Computer, 33(4), 58–60.https://doi.org/10.1109/2.839322 
LibreCat: /record/6507
DOI: 10.1109/2.839322

Eisenring, M., &; Platzner, M. (2000). Synthesis of Interfaces and Communication in Reconfigurable Embedded Systems. IEE Proceedings -- Computers &; Digital Techniques, 147, 159–165.https://doi.org/10.1049/ip-cdt:20000496 
LibreCat: /record/10606
DOI: 10.1049/ip-cdt:20000496

Platzner, M., Rinner, B., &; Weiss, R. (2000). Toward embedded qualitative simulation: a specialized computer architecture for QSim. IEEE Intelligent Systems, 15(2), 62–68.https://doi.org/10.1109/5254.850829 
LibreCat: /record/10725
DOI: 10.1109/5254.850829

Eisenring, M. H., &; Platzner, M. (2000). An Implementation Framework for Run-time Reconfigurable Systems. In Proceedings of the 2nd International Workshop on Engineering of Reconfigurable Hardware/Software Objects (ENREGLE) (pp. 151–157). CSREA Press.
LibreCat: /record/13609

Eisenring, M., &; Platzner, M. (2000). Optimization of Run-time Reconfigurable Embedded Systems. In Proceedings of the 10th International Workshop on Field Programmable Logic and Applications (FPL) (pp. 565–574). Springer.
LibreCat: /record/13610

Mencer, O., &; Platzner, M. (1999). Dynamic circuit generation for Boolean satisfiability in an object-oriented design environment. In Proceedings of the 32nd Annual Hawaii International Conference on Systems Sciences (HICSS-32). IEEE CS Press.https://doi.org/10.1109/hicss.1999.772883 
LibreCat: /record/13607
DOI: 10.1109/hicss.1999.772883

Eisenring, M., Platzner, M., &; Thiele, L. (1999). Communication Synthesis for Reconfigurable Embedded Systems. In Proceedings of the 9th International Workshop on Field Programmable Logic and Applications (FPL) (Vol. 1673, pp. 205–214). Springer.https://doi.org/10.1007/978-3-540-48302-1_21 
LibreCat: /record/13608
DOI: 10.1007/978-3-540-48302-1_21

Platzner, M. (1998). Reconfigurable Computer Architectures. E&;i Elektrotechnik Und Informationstechnik, 115, 143–148.
LibreCat: /record/10607

Platzner, M., &; Rinner, B. (1998). Design and Implementation of a Parallel Constraint Satisfaction Algorithm. International Journal of Computers &; Their Applications, 5, 106–116.
LibreCat: /record/10608

Platzner, M., Rinner, B., &; Weiss, R. (1998). A Distributed Computer Architecture for Fast Qualitative Simulation  (pp. 106–107). Texas Instruments, The Elite Yearbook 1997 - Digital Signal Processing Solutions from Europe’s leading Universities.
LibreCat: /record/13464

Platzner, M., &; De Micheli, G. (1998). Acceleration of satisfiability algorithms by reconfigurable hardware. In Proceedings of the 8th International Workshop on Field Programmable Logic and Applications (FPL)  (pp. 69–78). Berlin, Heidelberg: Springer .https://doi.org/10.1007/bfb0055234 
LibreCat: /record/13606
DOI: 10.1007/bfb0055234

Platzner, M., Rinner, B., &; Weiss, R. (1997). A Computer Architecture to Support Qualitative Simulation in Industrial Applications. E &; i Elektrotechnik Und Informationstechnik, 114, 13–18.
LibreCat: /record/10609

Platzner, M., Rinner, B., &; Weiss, R. (1997). Parallel qualitative simulation. Simulation Practice and Theory, 5(7–8), 623–638.https://doi.org/10.1016/s0928-4869(97)00008-6 
LibreCat: /record/10724
DOI: 10.1016/s0928-4869(97)00008-6

Platzner, M., &; Peters, L. (1997). Fast Signature Segmentation on a Multi-DSP Architecture. In Proceedings of the SPIE: Conference on Parallel and Distributed Methods for Image Processing (Vol. 3166).
LibreCat: /record/13603

Röwekamp, T., Platzner, M., &; Peters, L. (1997). Specialized Architectures for Optical Flow Computation: A Performance Comparison of ASIC, DSP, and Multi-DSP. In Proceedings of the 8th International Conference on Signal Processing Applications &; Technology (ICSPAT) (pp. 829–833).
LibreCat: /record/13604

Lind, E., Platzner, M., &; Rinner, B. (1996). A Multi-DSP System with Dynamically Reconfigurable Processors. In Proceedings of the 7th International Conference on Signal Processing Applications &; Technology (ICSPAT).
LibreCat: /record/13602

Platzner, M., Rinner, B., &; Weiss, R. (1995). Exploiting Parallelism in Constraint Satisfaction for Qualitative Simulation. J.UCS Journal of Universal Computer Science, 12, 811–820.
LibreCat: /record/10610

Platzner, M., Rinner, B., &; Weiss, R. (1995). A Distributed Computer Architecture for Qualitative Simulation based on a Multi-DSP and FPGAs. In Proceedings of the 3rd Euromicro Workshop on Parallel and Distributed Processing  (pp. 311–318). IEEE CS Press.
LibreCat: /record/13469

Brenner, E., Ginthör-Kalcsics, R., Hranitzky, R., Platzner, M., Rinner, B., Steger, C., &; Weiss, R. (1995). High-Performance Simulators Based on Multi-TM0. In Proceedings of the 5th Annual Texas Instruments TM0 Educators Conference.
LibreCat: /record/13470

Friedl, G., Platzner, M., &; Rinner, B. (1995). A Special-Purpose Coprocessor for Qualitative Simulation. In Proceedings of the EURO-PAR’95 International Conference on Parallel Processing (pp. 695–698). Springer International Publishing.
LibreCat: /record/13471

Platzner, M., Rinner, B., &; Weiss, R. (1995). Parallel Qualitative Simulation. In Proceedings of the EUROSIM Congress (pp. 231–236). Elsevier.
LibreCat: /record/13472