Distributed Simulation of mobile Robots using EyeSim
T. Ceylan, C. Yalcin, Distributed Simulation of Mobile Robots Using EyeSim, Paderborn University, 2007.
LibreCat: /record/10643

Server-based execution of periodic tasks on dynamically reconfigurable hardware
K. Danne, R. Mühlenbernd, M. Platzner, IET Computers Digital Techniques 1 (2007) 295–302.
LibreCat: /record/10646
DOI: 10.1049/iet-cdt:20060186

A Comparison of Multi-Objective Evolutionary Algorithms for Automated Circuit Design and Optimization
B. Defo, A Comparison of Multi-Objective Evolutionary Algorithms for Automated Circuit Design and Optimization, Paderborn University, 2007.
LibreCat: /record/10647

Entwurf und Implementierung einer RocketIO-basierten Kommunikationsschnittstelle für Multi-FPGA Systeme
S. Döhre, Entwurf Und Implementierung Einer RocketIO-Basierten Kommunikationsschnittstelle Für Multi-FPGA Systeme, Paderborn University, 2007.
LibreCat: /record/10648

Toward Self-adaptive Embedded Systems: Multi-objective Hardware Evolution
P. Kaufmann, M. Platzner, in: Architecture of Computing Systems (ARCS), Springer, 2007, pp. 199–208.
LibreCat: /record/10689

VHDL-Implementierung eines Clustering-Verfahrens für multikriterielle Optimierungsalgorithmen
R. Meiche, VHDL-Implementierung Eines Clustering-Verfahrens Für Multikriterielle Optimierungsalgorithmen, Paderborn University, 2007.
LibreCat: /record/10709

Bildverarbeitungs-Architekturen und -Bibliotheken für das rekonfigurierbare Betriebssystem ReconOS
W. Reisch, Bildverarbeitungs-Architekturen Und -Bibliotheken Für Das Rekonfigurierbare Betriebssystem ReconOS, Paderborn University, 2007.
LibreCat: /record/10728

Konzeption und Implementierung einer Microsoft Windows CE 5.0 Plattform für ein ARM-basiertes eingebettetes Rechnersystem
E. Rethmeier, Konzeption Und Implementierung Einer Microsoft Windows CE 5.0 Plattform Für Ein ARM-Basiertes Eingebettetes Rechnersystem, Paderborn University, 2007.
LibreCat: /record/10729

Accelerating the Cube Cut Problem with an FPGA-Augmented Compute Cluster
T. Schumacher, E. Lübbers, P. Kaufmann, M. Platzner, in: Proceedings of the ParaFPGA Symposium, International Conference on Parallel Computing: Architectures, Algorithms and Applications (PARCO), IOS Press, 2007, pp. 749–756.
LibreCat: /record/10735

A Many-Core Implementation Based on the Reconfigurable Mesh Model
H. Giefers, M. Platzner, in: Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL), IEEE, 2007.
LibreCat: /record/13627
DOI: 10.1109/fpl.2007.4380623

ReconOS: An RTOS Supporting Hard-and Software Threads
E. Lübbers, M. Platzner, in: Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL), IEEE, 2007.
LibreCat: /record/13628
DOI: 10.1109/fpl.2007.4380686

Optimal Temporal Partitioning based on Slowdown and Retiming
C. Plessl, M. Platzner, L. Thiele, in: Proc. Int. Conf. on Field Programmable Technology (ICFPT), IEEE Computer Society, 2006, pp. 345–348.
LibreCat: /record/2401
DOI: 10.1109/FPT.2006.270344

Multi-objective Intrinsic Hardware Evolution
P. Kaufmann, M. Platzner, in: Intl. Conf. Military Applications of Programmable Logic Devices (MAPLD), 2006.
LibreCat: /record/10688

FPGA-Implementierung eines server-basierten Schedulers für periodische Hardwaretasks
R. Mühlenbernd, FPGA-Implementierung Eines Server-Basierten Schedulers Für Periodische Hardwaretasks, Paderborn University, 2006.
LibreCat: /record/10716

Executing Hardware Tasks on Dynamically Reconfigurable Devices under Real-time Conditions
K. Danne, R. Mühlenbernd, M. Platzner, in: Proceedings of the 16th International Conference on Field Programmable Logic and Applications (FPL), IEEE, 2006.
LibreCat: /record/13624

An EDF Schedulability Test for Periodic Tasks on Reconfigurable Hardware Devices
K. Danne, M. Platzner, in: In ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES), 2006.
LibreCat: /record/13625

Partitioned Scheduling of Periodic Real-time Tasks onto Reconfigurable Hardware
K. Danne, M. Platzner, in: Proceedings of the 13th Reconfigurable Architectures Workshop (RAW), IEEE CS Press, 2006.
LibreCat: /record/13626

Zippy – A coarse-grained reconfigurable array with support for hardware virtualization
C. Plessl, M. Platzner, in: Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), IEEE Computer Society, 2005, pp. 213–218.
LibreCat: /record/2411
DOI: 10.1109/ASAP.2005.69

System-level performance evaluation of reconfigurable processors
R. Enzler, C. Plessl, M. Platzner, Microprocessors and Microsystems 29 (2005) 63–73.
LibreCat: /record/2412
DOI: 10.1016/j.micpro.2004.06.004

Periodic real-time scheduling for FPGA computers
K. Danne, M. Platzner, in: Proceedings of the Third International Workshop on Intelligent Solutions in Embedded Systems (WISES), 2005.
LibreCat: /record/13621
DOI: 10.1109/wises.2005.1438720

Memory-demanding Periodic Real-time Applications on FPGA Computers
K. Danne, M. Platzner, in: Work-in-Progress Proceedings of the 17th Euromicro Conference on Real-Time Systems (ECRTS), 2005.
LibreCat: /record/13622

A heuristic approach to schedule periodic real-time tasks on reconfigurable hardware
K. Danne, M. Platzner, in: Proceedings of the 15th International Conference on Field Programmable Logic and Applications (FPL), IEEE CS Press, 2005.
LibreCat: /record/13623
DOI: 10.1109/fpl.2005.1515787

Virtualization of Hardware – Introduction and Survey
C. Plessl, M. Platzner, in: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2004, pp. 63–69.
LibreCat: /record/2415

Operating systems for reconfigurable embedded platforms: online scheduling of real-time tasks
C. Steiger, H. Walder, M. Platzner, IEEE Transactions on Computers 53 (2004) 1393–1407.
LibreCat: /record/10742
DOI: 10.1109/tc.2004.99

A Runtime Environment for Reconfigurable Hardware Operating Systems
H. Walder, M. Platzner, in: Proceedings of the 14th International Conference on Field Programmable Logic and Applications (FPL), Springer, Berlin, Heidelberg, 2004, pp. 831–835.
LibreCat: /record/13618
DOI: 10.1007/978-3-540-30117-2_84

XF-BOARD: A Prototyping Platform for Reconfigurable Hardware Operating Systems
H. Walder, S. Nobs, M. Platzner, in: Proceedings of the 4th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2004.
LibreCat: /record/13619

Efficient Execution of Process Networks on a Reconfigurable Hardware Virtual Machine
M. Dyer, M. Platzner, L. Thiele, in: Proceedings 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), IEEE CS Press, 2004.
LibreCat: /record/13620
DOI: 10.1109/fccm.2004.31

TKDM – A Reconfigurable Co-processor in a PC's Memory Slot
C. Plessl, M. Platzner, in: Proc. Int. Conf. on Field Programmable Technology (ICFPT), IEEE Computer Society, 2003, pp. 252–259.
LibreCat: /record/2418
DOI: 10.1109/FPT.2003.1275755

The Case for Reconfigurable Hardware in Wearable Computing
C. Plessl, R. Enzler, H. Walder, J. Beutel, M. Platzner, L. Thiele, G. Tröster, Personal and Ubiquitous Computing 7 (2003) 299–308.
LibreCat: /record/2419
DOI: 10.1007/s00779-003-0243-x

Instance-Specific Accelerators for Minimum Covering
C. Plessl, M. Platzner, Journal of Supercomputing 26 (2003) 109–129.
LibreCat: /record/2420
DOI: 10.1023/a:1024443416592

Virtualizing Hardware with Multi-Context Reconfigurable Arrays
R. Enzler, C. Plessl, M. Platzner, in: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), Springer, 2003, pp. 151–160.
LibreCat: /record/2421
DOI: 10.1007/b12007

Co-simulation of a Hybrid Multi-Context Architecture
R. Enzler, C. Plessl, M. Platzner, in: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2003, pp. 174–180.
LibreCat: /record/2422

Online scheduling for block-partitioned reconfigurable devices
H. Walder, M. Platzner, in: Proceedings Design, Automation and Test in Europe Conference (DATE), IEEE CS Press, 2003, pp. 290–295.
LibreCat: /record/13612
DOI: 10.1109/date.2003.1253622

Fast online task placement on FPGAs: free space partitioning and 2D-hashing
H. Walder, C. Steiger, M. Platzner, in: Proceedings International Parallel and Distributed Processing Symposium, IEEE CS Press, 2003.
LibreCat: /record/13613
DOI: 10.1109/ipdps.2003.1213329

Reconfigurable Hardware Operating Systems: From Design Concepts to Realizations
H. Walder, M. Platzner, in: Proceedings of the 3rd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2003, pp. 284–287.
LibreCat: /record/13614

Heuristics for Online Scheduling Real-Time Tasks to Partially Reconfigurable Devices
C. Steiger, H. Walder, M. Platzner, in: Proceedings of the 13th International Conference on Field Programmable Logic and Applications (FPL), Springer, Berlin, Heidelberg, 2003, pp. 575–584.
LibreCat: /record/13615
DOI: 10.1007/978-3-540-45234-8_56

Online scheduling and placement of real-time tasks to partially reconfigurable devices
C. Steiger, H. Walder, M. Platzner, L. Thiele, in: Proceedings 24th IEEE International Real-Time Systems Symposium (RTSS), IEEE CS Press, 2003, pp. 252–235.
LibreCat: /record/13617
DOI: 10.1109/real.2003.1253269

Reconfigurable Hardware in Wearable Computing Nodes
C. Plessl, R. Enzler, H. Walder, J. Beutel, M. Platzner, L. Thiele, in: Proc. Int. Symp. on Wearable Computers (ISWC), IEEE Computer Society, 2002, pp. 215–222.
LibreCat: /record/2423
DOI: 10.1109/ISWC.2002.1167250

Partially Reconfigurable Cores for Xilinx Virtex
M. Dyer, C. Plessl, M. Platzner, in: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), Springer, 2002, pp. 292–301.
LibreCat: /record/2424
DOI: 10.1007/3-540-46117-5

Custom Computing Machines for the Set Covering Problem
C. Plessl, M. Platzner, in: Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), IEEE Computer Society, 2002, pp. 163–172.
LibreCat: /record/2425
DOI: 10.1109/FPGA.2002.1106671

A Framework for Run-time Reconfigurable Systems
M. Eisenring, M. Platzner, The Journal of Supercomputing 21 (2002) 145–159.
LibreCat: /record/10651
DOI: 10.1023/a:1013627403946

Non-preemptive Multitasking on FPGAs: Task Placement and Footprint Transform
H. Walder, M. Platzner, in: Proceedings of the 2nd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2002, pp. 24–30.
LibreCat: /record/13611

Instance-Specific Accelerators for Minimum Covering
C. Plessl, M. Platzner, in: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2001, pp. 85–91.
LibreCat: /record/2428

Reconfigurable Processors for Handhelds and Wearables: Application Analysis
R. Enzler, M. Platzner, C. Plessl, L. Thiele, G. Tröster, in: Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III, 2001, pp. 135–146.
LibreCat: /record/2432
DOI: 10.1117/12.434376

Object-oriented domain specific compilers for programming FPGAs
O. Mencer, M. Platzner, M. Morf, M. J. Flynn, IEEE Transactions on Very Large Scale Integration (VLSI) Systems 9 (2001) 205–210.
LibreCat: /record/10713
DOI: 10.1109/92.920835

Dynamically Reconfigurable Processors
R. Enzler, M. Platzner, Dynamically Reconfigurable Processors, TELEMATIK, Zeitschrift des Telematik-Ingebieur-Verbandes 7(1), 2001.
LibreCat: /record/13463

Reconfigurable accelerators for combinatorial problems
M. Platzner, Computer 33 (2000) 58–60.
LibreCat: /record/6507
DOI: 10.1109/2.839322

Synthesis of Interfaces and Communication in Reconfigurable Embedded Systems
M. Eisenring, M. Platzner, IEE Proceedings -- Computers &; Digital Techniques 147 (2000) 159–165.
LibreCat: /record/10606
DOI: 10.1049/ip-cdt:20000496

Toward embedded qualitative simulation: a specialized computer architecture for QSim
M. Platzner, B. Rinner, R. Weiss, IEEE Intelligent Systems 15 (2000) 62–68.
LibreCat: /record/10725
DOI: 10.1109/5254.850829

An Implementation Framework for Run-time Reconfigurable Systems
M.H. Eisenring, M. Platzner, in: Proceedings of the 2nd International Workshop on Engineering of Reconfigurable Hardware/Software Objects (ENREGLE), CSREA Press, 2000, pp. 151–157.
LibreCat: /record/13609

Optimization of Run-time Reconfigurable Embedded Systems
M. Eisenring, M. Platzner, in: Proceedings of the 10th International Workshop on Field Programmable Logic and Applications (FPL), Springer, 2000, pp. 565–574.
LibreCat: /record/13610

Dynamic circuit generation for Boolean satisfiability in an object-oriented design environment
O. Mencer, M. Platzner, in: Proceedings of the 32nd Annual Hawaii International Conference on Systems Sciences (HICSS-32), IEEE CS Press, 1999.
LibreCat: /record/13607
DOI: 10.1109/hicss.1999.772883

Communication Synthesis for Reconfigurable Embedded Systems
M. Eisenring, M. Platzner, L. Thiele, in: Proceedings of the 9th International Workshop on Field Programmable Logic and Applications (FPL), Springer, 1999, pp. 205–214.
LibreCat: /record/13608
DOI: 10.1007/978-3-540-48302-1_21

Reconfigurable Computer Architectures
M. Platzner, E&;i Elektrotechnik Und Informationstechnik 115 (1998) 143–148.
LibreCat: /record/10607

Design and Implementation of a Parallel Constraint Satisfaction Algorithm
M. Platzner, B. Rinner, International Journal of Computers &; Their Applications 5 (1998) 106–116.
LibreCat: /record/10608

A Distributed Computer Architecture for Fast Qualitative Simulation 
M. Platzner, B. Rinner, R. Weiss, A Distributed Computer Architecture for Fast Qualitative Simulation , Texas Instruments, The Elite Yearbook 1997 - Digital Signal Processing Solutions from Europe’s leading Universities, 1998.
LibreCat: /record/13464

Acceleration of satisfiability algorithms by reconfigurable hardware
M. Platzner, G. De Micheli, in: Proceedings of the 8th International Workshop on Field Programmable Logic and Applications (FPL) , Springer , Berlin, Heidelberg, 1998, pp. 69–78.
LibreCat: /record/13606
DOI: 10.1007/bfb0055234

A Computer Architecture to Support Qualitative Simulation in Industrial Applications
M. Platzner, B. Rinner, R. Weiss, E &; i Elektrotechnik Und Informationstechnik 114 (1997) 13–18.
LibreCat: /record/10609

Parallel qualitative simulation
M. Platzner, B. Rinner, R. Weiss, Simulation Practice and Theory 5 (1997) 623–638.
LibreCat: /record/10724
DOI: 10.1016/s0928-4869(97)00008-6

Fast Signature Segmentation on a Multi-DSP Architecture
M. Platzner, L. Peters, in: Proceedings of the SPIE: Conference on Parallel and Distributed Methods for Image Processing, 1997.
LibreCat: /record/13603

Specialized Architectures for Optical Flow Computation: A Performance Comparison of ASIC, DSP, and Multi-DSP
T. Röwekamp, M. Platzner, L. Peters, in: Proceedings of the 8th International Conference on Signal Processing Applications &; Technology (ICSPAT), 1997, pp. 829–833.
LibreCat: /record/13604

A Multi-DSP System with Dynamically Reconfigurable Processors
E. Lind, M. Platzner, B. Rinner, in: Proceedings of the 7th International Conference on Signal Processing Applications &; Technology (ICSPAT), 1996.
LibreCat: /record/13602

Exploiting Parallelism in Constraint Satisfaction for Qualitative Simulation
M. Platzner, B. Rinner, R. Weiss, J.UCS Journal of Universal Computer Science 12 (1995) 811–820.
LibreCat: /record/10610

A Distributed Computer Architecture for Qualitative Simulation based on a Multi-DSP and FPGAs
M. Platzner, B. Rinner, R. Weiss, in: Proceedings of the 3rd Euromicro Workshop on Parallel and Distributed Processing , IEEE CS Press, 1995, pp. 311–318.
LibreCat: /record/13469

High-Performance Simulators Based on Multi-TM0
E. Brenner, R. Ginthör-Kalcsics, R. Hranitzky, M. Platzner, B. Rinner, C. Steger, R. Weiss, in: Proceedings of the 5th Annual Texas Instruments TM0 Educators Conference, 1995.
LibreCat: /record/13470

A Special-Purpose Coprocessor for Qualitative Simulation
G. Friedl, M. Platzner, B. Rinner, in: Proceedings of the EURO-PAR’95 International Conference on Parallel Processing, Springer International Publishing, 1995, pp. 695–698.
LibreCat: /record/13471

Parallel Qualitative Simulation
M. Platzner, B. Rinner, R. Weiss, in: Proceedings of the EUROSIM Congress, Elsevier, 1995, pp. 231–236.
LibreCat: /record/13472

Improving Performance of the Qualitative Simulator QSIM - Design and Implementation of a Specialized Computer Architecture
M. Platzner, B. Rinner, in: Proceedings of the PDCS International Conference on Parallel and Distributed Computing Systems, ISCA, 1995, pp. 494–501.
LibreCat: /record/13473

High-Performance Qualitative Simulation on a Multi-DSP Architecture
M. Platzner, B. Rinner, in: Proceedings of the 6th International Conference on Signal Processing Applications &; Technology (ICSPAT), 1995.
LibreCat: /record/13474

Design and Implementation of Adaptive Digital Filters on a Multi-TM0 System
R. Hranitzky, M. Platzner, in: Proceedings of the 6th International Conference on Signal Processing Applications &; Technology (ICSPAT), 1995.
LibreCat: /record/13484

Experimental Evaluation of Multi-DSP Architectures in High Performance Applications
M. Platzner, C. Steger, R. Weiss, in: Proceedings of the 7th Mediterranean Electrotechnical Conference, IEEE Press, 1994.
LibreCat: /record/13468

Erfahrungen mit einer Multi-Signalprozessorarchitektur (TM0)
M. Platzner, C. Steger, Mikroelektronik (1993).
LibreCat: /record/13466

Performance Measurements on a Multi-DSP Architecture with TM0
M. Platzner, C. Steger, R. Weiss, in: Proceedings of the 4th International Conference on Signal Processing Applications &; Technology (ICSPAT), DSP Associates, 1993.
LibreCat: /record/13467

Experimental Results to Interprocessor Communication in Distributed Transputer-Systems
R. Ginthör, M. Platzner, R. Weiss, in: Proceedings of the 1st Austrian-Hungarian Workshop on Transputer Applications, 1992, pp. 45–54.
LibreCat: /record/13465