M. Dyer, M. Platzner, and L. Thiele, “Efficient Execution of Process Networks on a Reconfigurable Hardware Virtual Machine,” in Proceedings 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), 2004.
LibreCat: /record/13620
DOI: 10.1109/fccm.2004.31

C. Plessl and M. Platzner, “TKDM – A Reconfigurable Co-processor in a PC’s Memory Slot,” in Proc. Int. Conf. on Field Programmable Technology (ICFPT), 2003, pp. 252–259.
LibreCat: /record/2418
DOI: 10.1109/FPT.2003.1275755

C. Plessl et al., “The Case for Reconfigurable Hardware in Wearable Computing,” Personal and Ubiquitous Computing, vol. 7, no. 5, pp. 299–308, 2003.
LibreCat: /record/2419
DOI: 10.1007/s00779-003-0243-x

C. Plessl and M. Platzner, “Instance-Specific Accelerators for Minimum Covering,” Journal of Supercomputing, vol. 26, no. 2, pp. 109–129, 2003.
LibreCat: /record/2420
DOI: 10.1023/a:1024443416592

R. Enzler, C. Plessl, and M. Platzner, “Virtualizing Hardware with Multi-Context Reconfigurable Arrays,” in Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), 2003, vol. 2778, pp. 151–160.
LibreCat: /record/2421
DOI: 10.1007/b12007

R. Enzler, C. Plessl, and M. Platzner, “Co-simulation of a Hybrid Multi-Context Architecture,” in Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2003, pp. 174–180.
LibreCat: /record/2422

H. Walder and M. Platzner, “Online scheduling for block-partitioned reconfigurable devices,” in Proceedings Design, Automation and Test in Europe Conference (DATE), 2003, pp. 290–295.
LibreCat: /record/13612
DOI: 10.1109/date.2003.1253622

H. Walder, C. Steiger, and M. Platzner, “Fast online task placement on FPGAs: free space partitioning and 2D-hashing,” in Proceedings International Parallel and Distributed Processing Symposium, 2003.
LibreCat: /record/13613
DOI: 10.1109/ipdps.2003.1213329

H. Walder and M. Platzner, “Reconfigurable Hardware Operating Systems: From Design Concepts to Realizations,” in Proceedings of the 3rd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2003, pp. 284–287.
LibreCat: /record/13614

C. Steiger, H. Walder, and M. Platzner, “Heuristics for Online Scheduling Real-Time Tasks to Partially Reconfigurable Devices,” in Proceedings of the 13th International Conference on Field Programmable Logic and Applications (FPL), 2003, pp. 575–584.
LibreCat: /record/13615
DOI: 10.1007/978-3-540-45234-8_56

C. Steiger, H. Walder, M. Platzner, and L. Thiele, “Online scheduling and placement of real-time tasks to partially reconfigurable devices,” in Proceedings 24th IEEE International Real-Time Systems Symposium (RTSS), 2003, pp. 252–235.
LibreCat: /record/13617
DOI: 10.1109/real.2003.1253269

C. Plessl, R. Enzler, H. Walder, J. Beutel, M. Platzner, and L. Thiele, “Reconfigurable Hardware in Wearable Computing Nodes,” in Proc. Int. Symp. on Wearable Computers (ISWC), 2002, pp. 215–222.
LibreCat: /record/2423
DOI: 10.1109/ISWC.2002.1167250

M. Dyer, C. Plessl, and M. Platzner, “Partially Reconfigurable Cores for Xilinx Virtex,” in Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), 2002, vol. 2438, pp. 292–301.
LibreCat: /record/2424
DOI: 10.1007/3-540-46117-5

C. Plessl and M. Platzner, “Custom Computing Machines for the Set Covering Problem,” in Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), 2002, pp. 163–172.
LibreCat: /record/2425
DOI: 10.1109/FPGA.2002.1106671

M. Eisenring and M. Platzner, “A Framework for Run-time Reconfigurable Systems,” The Journal of Supercomputing, vol. 21, no. 2, pp. 145–159, 2002.
LibreCat: /record/10651
DOI: 10.1023/a:1013627403946

H. Walder and M. Platzner, “Non-preemptive Multitasking on FPGAs: Task Placement and Footprint Transform,” in Proceedings of the 2nd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2002, pp. 24–30.
LibreCat: /record/13611

C. Plessl and M. Platzner, “Instance-Specific Accelerators for Minimum Covering,” in Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2001, pp. 85–91.
LibreCat: /record/2428

R. Enzler, M. Platzner, C. Plessl, L. Thiele, and G. Tröster, “Reconfigurable Processors for Handhelds and Wearables: Application Analysis,” in Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III, 2001, vol. 4525, pp. 135–146.
LibreCat: /record/2432
DOI: 10.1117/12.434376

O. Mencer, M. Platzner, M. Morf, and M. J. Flynn, “Object-oriented domain specific compilers for programming FPGAs,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 9, no. 1, pp. 205–210, 2001.
LibreCat: /record/10713
DOI: 10.1109/92.920835

R. Enzler and M. Platzner, Dynamically Reconfigurable Processors. TELEMATIK, Zeitschrift des Telematik-Ingebieur-Verbandes 7(1), 2001.
LibreCat: /record/13463

M. Platzner, “Reconfigurable accelerators for combinatorial problems,” Computer, vol. 33, no. 4, pp. 58–60, 2000.
LibreCat: /record/6507
DOI: 10.1109/2.839322

M. Eisenring and M. Platzner, “Synthesis of Interfaces and Communication in Reconfigurable Embedded Systems,” IEE Proceedings -- Computers &; Digital Techniques, vol. 147, pp. 159–165, 2000.
LibreCat: /record/10606
DOI: 10.1049/ip-cdt:20000496

M. Platzner, B. Rinner, and R. Weiss, “Toward embedded qualitative simulation: a specialized computer architecture for QSim,” IEEE Intelligent Systems, vol. 15, no. 2, pp. 62–68, 2000.
LibreCat: /record/10725
DOI: 10.1109/5254.850829

M. H. Eisenring and M. Platzner, “An Implementation Framework for Run-time Reconfigurable Systems,” in Proceedings of the 2nd International Workshop on Engineering of Reconfigurable Hardware/Software Objects (ENREGLE), 2000, pp. 151–157.
LibreCat: /record/13609

M. Eisenring and M. Platzner, “Optimization of Run-time Reconfigurable Embedded Systems,” in Proceedings of the 10th International Workshop on Field Programmable Logic and Applications (FPL), 2000, pp. 565–574.
LibreCat: /record/13610

O. Mencer and M. Platzner, “Dynamic circuit generation for Boolean satisfiability in an object-oriented design environment,” in Proceedings of the 32nd Annual Hawaii International Conference on Systems Sciences (HICSS-32), 1999.
LibreCat: /record/13607
DOI: 10.1109/hicss.1999.772883

M. Eisenring, M. Platzner, and L. Thiele, “Communication Synthesis for Reconfigurable Embedded Systems,” in Proceedings of the 9th International Workshop on Field Programmable Logic and Applications (FPL), 1999, vol. 1673, pp. 205–214.
LibreCat: /record/13608
DOI: 10.1007/978-3-540-48302-1_21

M. Platzner, “Reconfigurable Computer Architectures,” e&;i Elektrotechnik und Informationstechnik, vol. 115, pp. 143–148, 1998.
LibreCat: /record/10607

M. Platzner and B. Rinner, “Design and Implementation of a Parallel Constraint Satisfaction Algorithm,” International Journal of Computers &; Their Applications, vol. 5, pp. 106–116, 1998.
LibreCat: /record/10608

M. Platzner, B. Rinner, and R. Weiss, A Distributed Computer Architecture for Fast Qualitative Simulation . Texas Instruments, The Elite Yearbook 1997 - Digital Signal Processing Solutions from Europe’s leading Universities, 1998, pp. 106–107.
LibreCat: /record/13464

M. Platzner and G. De Micheli, “Acceleration of satisfiability algorithms by reconfigurable hardware,” in Proceedings of the 8th International Workshop on Field Programmable Logic and Applications (FPL) , 1998, pp. 69–78.
LibreCat: /record/13606
DOI: 10.1007/bfb0055234

M. Platzner, B. Rinner, and R. Weiss, “A Computer Architecture to Support Qualitative Simulation in Industrial Applications,” e &; i Elektrotechnik und Informationstechnik, vol. 114, pp. 13–18, 1997.
LibreCat: /record/10609

M. Platzner, B. Rinner, and R. Weiss, “Parallel qualitative simulation,” Simulation Practice and Theory, vol. 5, no. 7–8, pp. 623–638, 1997.
LibreCat: /record/10724
DOI: 10.1016/s0928-4869(97)00008-6

M. Platzner and L. Peters, “Fast Signature Segmentation on a Multi-DSP Architecture,” in Proceedings of the SPIE: Conference on Parallel and Distributed Methods for Image Processing, 1997, vol. 3166.
LibreCat: /record/13603

T. Röwekamp, M. Platzner, and L. Peters, “Specialized Architectures for Optical Flow Computation: A Performance Comparison of ASIC, DSP, and Multi-DSP,” in Proceedings of the 8th International Conference on Signal Processing Applications &; Technology (ICSPAT), 1997, pp. 829–833.
LibreCat: /record/13604

E. Lind, M. Platzner, and B. Rinner, “A Multi-DSP System with Dynamically Reconfigurable Processors,” in Proceedings of the 7th International Conference on Signal Processing Applications &; Technology (ICSPAT), 1996.
LibreCat: /record/13602

M. Platzner, B. Rinner, and R. Weiss, “Exploiting Parallelism in Constraint Satisfaction for Qualitative Simulation,” J.UCS Journal of Universal Computer Science, vol. 12, pp. 811–820, 1995.
LibreCat: /record/10610

M. Platzner, B. Rinner, and R. Weiss, “A Distributed Computer Architecture for Qualitative Simulation based on a Multi-DSP and FPGAs,” in Proceedings of the 3rd Euromicro Workshop on Parallel and Distributed Processing , 1995, pp. 311–318.
LibreCat: /record/13469

E. Brenner et al., “High-Performance Simulators Based on Multi-TM0,” in Proceedings of the 5th Annual Texas Instruments TM0 Educators Conference, 1995.
LibreCat: /record/13470

G. Friedl, M. Platzner, and B. Rinner, “A Special-Purpose Coprocessor for Qualitative Simulation,” in Proceedings of the EURO-PAR’95 International Conference on Parallel Processing, 1995, pp. 695–698.
LibreCat: /record/13471

M. Platzner, B. Rinner, and R. Weiss, “Parallel Qualitative Simulation,” in Proceedings of the EUROSIM Congress, 1995, pp. 231–236.
LibreCat: /record/13472

M. Platzner and B. Rinner, “Improving Performance of the Qualitative Simulator QSIM - Design and Implementation of a Specialized Computer Architecture,” in Proceedings of the PDCS International Conference on Parallel and Distributed Computing Systems, 1995, pp. 494–501.
LibreCat: /record/13473

M. Platzner and B. Rinner, “High-Performance Qualitative Simulation on a Multi-DSP Architecture,” in Proceedings of the 6th International Conference on Signal Processing Applications &; Technology (ICSPAT), 1995.
LibreCat: /record/13474

R. Hranitzky and M. Platzner, “Design and Implementation of Adaptive Digital Filters on a Multi-TM0 System,” in Proceedings of the 6th International Conference on Signal Processing Applications &; Technology (ICSPAT), 1995.
LibreCat: /record/13484

M. Platzner, C. Steger, and R. Weiss, “Experimental Evaluation of Multi-DSP Architectures in High Performance Applications,” in Proceedings of the 7th Mediterranean Electrotechnical Conference, 1994.
LibreCat: /record/13468

M. Platzner and C. Steger, “Erfahrungen mit einer Multi-Signalprozessorarchitektur (TM0),” Mikroelektronik, 1993.
LibreCat: /record/13466

M. Platzner, C. Steger, and R. Weiss, “Performance Measurements on a Multi-DSP Architecture with TM0,” in Proceedings of the 4th International Conference on Signal Processing Applications &; Technology (ICSPAT), 1993.
LibreCat: /record/13467

R. Ginthör, M. Platzner, and R. Weiss, “Experimental Results to Interprocessor Communication in Distributed Transputer-Systems,” in Proceedings of the 1st Austrian-Hungarian Workshop on Transputer Applications, 1992, pp. 45–54.
LibreCat: /record/13465