Lienen, Christian, et al. “ReconROS: Flexible Hardware Acceleration for RO Applications.” Proceedings of the 2020 International Conference on Field-Programmable Technology (FPT), 2020.
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Thiele, Simon. Implementing Machine Learning Functions as PYNQ FPGA Overlays. 2020.
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Jaganath, Vivek. Extension and Evaluation of Python-Based High-Level Synthesis Tool Flows. 2020.
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Hansmeier, Tim, et al. “An Adaption Mechanism for the Error Threshold of XCSF.”10.1145/3377929.3398106__GECCO ’20: Proceedings of the Genetic and Evolutionary Computation Conference Companion, Association for Computing Machinery (ACM), 2020, pp. 1756–64, doi:10.1145/3377929.3398106.
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Anwer, Jahanzeb, et al. “Dynamic Reliability Management for FPGA-Based Systems.”10.1155/2020/2808710__International Journal of Reconfigurable Computing, 2020, pp. 1–19, doi:10.1155/2020/2808710.
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Bellman, K., et al. “Self-Aware Cyber-Physical Systems.” ACM Transactions on Cyber-Physical Systems, vol. Accepted for Publication, 2020, pp. 1–24.
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Awais, Muhammad, et al. “A Hybrid Synthesis Methodology for Approximate Circuits.”10.1145/3386263.3406952__Proceedings of the 30th ACM Great Lakes Symposium on VLSI (GLSVLSI) 2020, ACM, 2020, pp. 421–26, doi:10.1145/3386263.3406952.
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Hansmeier, Tim, et al. “Enabling XCSF to Cope with Dynamic Environments via an Adaptive Error Threshold.”10.1145/3377929.3389968__GECCO ’20: Proceedings of the Genetic and Evolutionary Computation Conference Companion, Association for Computing Machinery (ACM), 2020, pp. 125–26, doi:10.1145/3377929.3389968.
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Lösch, Achim, and Marco Platzner. “MigHEFT: DAG-Based Scheduling of Migratable Tasks on Heterogeneous Compute Nodes.”10.1109/ipdpsw50202.2020.00012__2020 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), 2020, doi:10.1109/ipdpsw50202.2020.00012.
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Jentzsch, Felix P. Design and Implementation of a ReconOS-Based TensorFlow Lite Delegate Architecture. 2020.
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Lösch, Achim, and Marco Platzner. “MigHEFT: DAG-Based Scheduling of Migratable Tasks on Heterogeneous Compute Nodes.”10.1109/IPDPSW50202.2020.00012__2020 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), 2020, pp. 6–16, doi:10.1109/IPDPSW50202.2020.00012.
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Witschen, Linus Matthias, et al. “CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit Generation.”10.1016/j.microrel.2019.04.003__Microelectronics Reliability, vol. 99, Elsevier, 2019, pp. 277–90, doi:10.1016/j.microrel.2019.04.003.
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Witschen, Linus Matthias, et al. “Jump Search: A Fast Technique for the Synthesis of Approximate Circuits.” Fourth Workshop on Approximate Computing (AxC 2019).
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Witschen, Linus Matthias, et al. “Jump Search: A Fast Technique for the Synthesis of Approximate Circuits.”10.1145/3299874.3317998__Proceedings of the 2019 on Great Lakes Symposium on VLSI  - GLSVLSI ’19, ACM, 2019, doi:10.1145/3299874.3317998.
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Boschmann, Alexander, et al. “Zynq-Based Acceleration of Robust High Density Myoelectric Signal Processing.”10.1016/j.jpdc.2018.07.004__Journal of Parallel and Distributed Computing, vol. 123, Elsevier, 2019, pp. 77–89, doi:10.1016/j.jpdc.2018.07.004.
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Hansmeier, Tim, et al. “An Accelerator for Resolution Proof Checking Based on FPGA and Hybrid Memory Cube Technology.”10.1007/s11265-018-1435-y__Journal of Signal Processing Systems, vol. 91, no. 11, 2019, pp. 1259–72, doi:10.1007/s11265-018-1435-y.
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Ho, Nam, et al. “Optimization of Application-Specific L1 Cache Translation Functions of the LEON3 Processor.” World Congress on Nature and Biologically Inspired Computing (NaBIC), Springer, 2019.
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Kumar Jeyakumar, Shankar. Incremental Learning with Support Vector Machine on Embedded Platforms. 2019.
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Keerthipati, Monica. A Bitstream-Level Proof-Carrying Hardware Technique for Information Flow Tracking. Universität Paderborn, 2019.
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Sabu, Nithin S. FPGA Acceleration of String Search Techniques in Huge Data Sets. Paderborn University, 2019.
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Mehta, Jinay. Multithreaded Software/Hardware Programming with ReconOS/FreeRTOS on a Reconfc03gurable System-on-Chip. 2019.
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Hansmeier, Tim. Autonomous Operation of High-Performance Compute Nodes through Self-Awareness and Learning Classifiers. Universität Paderborn, 2019.
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Guettatfi, Zakarya, et al. “An Approach for Mapping Periodic Real-Time Tasks to Reconfigurable Hardware.”10.1109/ipdpsw.2019.00027__2019 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), IEEE, 2019, doi:10.1109/ipdpsw.2019.00027.
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Ahmed, Qazi Arbab, et al. “Proof-Carrying Hardware Versus the Stealthy Malicious LUT Hardware Trojan.”10.1007/978-3-030-17227-5_10__Applied Reconfigurable Computing, edited by Christian Hochberger et al., vol. 11444, Springer International Publishing, 2019, pp. 127–36, doi:10.1007/978-3-030-17227-5_10.
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Lienen, Christian. Implementing a Real-Time System on a Platform FPGA Operated with ReconOS. Universität Paderborn.
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Platzner, Marco, and Christian Plessl. “FPGAs im Rechenzentrum.”10.1007/s00287-019-01187-w__Informatik Spektrum, 2019, doi:10.1007/s00287-019-01187-w.
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Mehta, Jinay D. Multithreaded Software/Hardware Programming with ReconOS/FreeRTOS on a Reconfigurable System-on-Chip. 2019.
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Lösch, Achim, et al. “Ampehre: An Open Source Measurement Framework for Heterogeneous Compute Nodes.”10.1007/978-3-319-77610-1_6__Proceedings of the International Conference on Architecture of Computing Systems (ARCS), vol. 10793, Springer International Publishing, 2018, pp. 73–84, doi:10.1007/978-3-319-77610-1_6.
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Schnuer, Jan-Philip. Static Scheduling Algorithms for Heterogeneous Compute Nodes. Universität Paderborn, 2018.
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Croce, Marcel. Evaluation of OpenCL-Based Compilation for FPGAs. Universität Paderborn, 2018.
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Hansmeier, Tim, et al. “An FPGA/HMC-Based Accelerator for Resolution Proof Checking.”10.1007/978-3-319-78890-6_13__ARC 2018: Applied Reconfigurable Computing. Architectures, Tools, and Applications, vol. 10824, Springer International Publishing, 2018, pp. 153–65, doi:10.1007/978-3-319-78890-6_13.
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Witschen, Linus Matthias, et al. “CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit Generation.” Third Workshop on Approximate Computing (AxC 2018).
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Ho, Nam. FPGA-Based Reconfigurable Cache Mapping Schemes: Design and Optimization. Universität Paderborn, 2018, doi:10.17619/UNIPB/1-376.
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Witschen, Linus Matthias, et al. “Making the Case for Proof-Carrying Approximate Circuits.” 4th Workshop On Approximate Computing (WAPCO 2018), 2018.
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Lösch, Achim, and Marco Platzner. “A Highly Accurate Energy Model for Task Execution on Heterogeneous Compute Nodes.”10.1109/asap.2018.8445098__2018 IEEE 29th International Conference on Application-Specific Systems, Architectures and Processors (ASAP), IEEE, 2018, doi:10.1109/asap.2018.8445098.
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Awais, Muhammad, et al. “An MCTS-Based Framework for Synthesis of Approximate Circuits.”10.1109/VLSI-SoC.2018.8645026__26th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 2018, pp. 219–24, doi:10.1109/VLSI-SoC.2018.8645026.
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Clausing, Lennart. Development of a Hardware / Software Codesign for Sonification of LIDAR-Based Sensor Data. Ruhr-University Bochum, 2018.
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Jentzsch, Felix Paul. Enforcing IP Core Connection Properties with Verifiable Security Monitors. Universität Paderborn, 2018.
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Ghribi, Ines, et al. “R-Codesign: Codesign Methodology for Real-Time Reconfigurable Embedded Systems Under Energy Constraints.”10.1109/access.2018.2799852__IEEE Access, 2018, pp. 14078–92, doi:10.1109/access.2018.2799852.
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Hansmeier, Tim. An FPGA Accelerator for Checking Resolution Proofs. Universität Paderborn, 2017.
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Witschen, Linus Matthias. A Framework for the Synthesis of Approximate Circuits. Universität Paderborn, 2017.
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Knorr, Christoph. OpenCL-basierte Videoverarbeitung auf heterogenen Rechenknoten. Universität Paderborn, 2017.
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Shen, Cong, et al. “Three-Stage Power System Restoration Methodology Considering Renewable Energies.”10.1016/j.ijepes.2017.07.007__Elsevier International Journal of Electrical Power and Energy Systems (IJEPES), vol. 94, 2017, pp. 287–99, doi:10.1016/j.ijepes.2017.07.007.
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Lösch, Achim, and Marco Platzner. “ReMinMin: A Novel Static Energy-Centric List Scheduling Approach Based on Real Measurements.”10.1109/ASAP.2017.7995272__Proceedings of the 28th Annual IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP), 2017, doi:10.1109/ASAP.2017.7995272.
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Isenberg, Tobias, et al. “Proof-Carrying Hardware via Inductive Invariants.”10.1145/3054743__ACM Transactions on Design Automation of Electronic Systems, no. 4, ACM, 2017, pp. 61:1--61:23, doi:10.1145/3054743.
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H.W. Leong, Philip, et al. “The First 25 Years of the FPL Conference – Significant Papers.”10.1145/2996468__ACM Transactions on Reconfigurable Technology and Systems, 2017, doi:10.1145/2996468.
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F. DeMara, Ronald, et al. “Innovation in Reconfigurable Computing Fabrics: From Devices to Architectures (Guest Editorial).”10.1109/TETC.2016.2641599__IEEE Transactions on Computers and IEEE Transactions on Emerging Topics in Computing, 2017, doi:10.1109/TETC.2016.2641599.
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Anwer, Jahanzeb, and Marco Platzner. “Evaluating Fault-Tolerance of Redundant FPGA Structures Using Boolean Difference Calculus.”10.1016/j.micpro.2017.06.002__Microprocessors and Microsystems, Elsevier, 2017, pp. 160–72, doi:10.1016/j.micpro.2017.06.002.
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Kaltschmidt, Christian. An AR-Based Training and Assessment System for Myoelectrical Prosthetic Control. Paderborn University, 2017.
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Boschmann, Alexander, et al. “A Zynq-Based Dynamically Reconfigurable High Density Myoelectric Prosthesis Controller.”10.23919/DATE.2017.7927137__Design, Automation and Test in Europe (DATE), 2017, doi:10.23919/DATE.2017.7927137.
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Riaz, Umair. Acceleration of Industrial Analytics Functions on a Platform FPGA. Paderborn University, 2017.
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Ho, Nam, et al. “Accurate Private/Shared Classification of Memory Accesses: A Run-Time Analysis System for the LEON3 Multi-Core Processor.”10.23919/DATE.2017.7927096__Proc. Design, Automation and Test in Europe Conf. (DATE), 2017, doi:10.23919/DATE.2017.7927096.
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Ho, Nam, et al. “Evolvable Caches: Optimization of Reconfigurable Cache Mappings for a LEON3/Linux-Based Multi-Core Processor.”10.1109/FPT.2017.8280144__2017 International Conference on Field Programmable Technology (ICFPT), 2017, pp. 215–18, doi:10.1109/FPT.2017.8280144.
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Shen, Cong, et al. “Three-Stage Power System Restoration Methodology Considering Renewable Energies.” Elsevier International Journal of Electrical Power and Energy Systems (IJEPES), 2017.
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Dietrich, Andreas. Reconfigurable Cryptographic Services. Paderborn University, 2017.
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Shen, Cong, et al. “Fast Network Restoration by Partitioning of Parallel Black Start Zones.”10.1049/joe.2017.0032__The Journal of Engineering, 2017, p. 19pp, doi:10.1049/joe.2017.0032.
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Squillero, Giovanni, et al. Applications of Evolutionary Computation - 20th European Conference, EvoApplications. Springer, 2017.
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Kaufmann, Paul, and Roman Kalkreuth. “Parametrizing Cartesian Genetic Programming: An Empirical Study.”10.1007/978-3-319-67190-1_26__KI 2017: Advances in Artificial Intelligence: 40th Annual German Conference on AI, Springer International Publishing, 2017, doi:10.1007/978-3-319-67190-1_26.
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Kaufmann, Paul, et al. “Evaluation Methodology for Complex Non-Deterministic Functions: A Case Study in Metaheuristic Optimization of Caches.”10.1109/AHS.2017.8046380__Adaptive Hardware and Systems (AHS), IEEE, 2017, doi:10.1109/AHS.2017.8046380.
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Kaufmann, Paul, and Roman Kalkreuth. “An Empirical Study on the Parametrization of Cartesian Genetic Programming.”10.1145/3067695.3075980__Genetic and Evolutionary Computation (GECCO), Compendium, ACM, 2017, doi:10.1145/3067695.3075980.
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Guettatfi, Zakarya, et al. “Computational Self-Awareness as Design Approach for Visual Sensor Nodes.”10.1109/ReCoSoC.2017.8016147__12th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC), 2017, pp. 1–8, doi:10.1109/ReCoSoC.2017.8016147.
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Ghribi, Ines, et al. “I-Codesign: A Codesign Methodology for Reconfigurable Embedded Systems.”10.1007/978-3-319-62569-0_8__Communications in Computer and Information Science, Springer , 2017, doi:10.1007/978-3-319-62569-0_8.
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Wiersema, Tobias, et al. “An Architecture and Design Tool Flow for Embedding a Virtual FPGA into a Reconfigurable System-on-Chip.”10.1016/j.compeleceng.2016.04.005__Computers &; Electrical Engineering, Elsevier, 2016, pp. 112--122, doi:10.1016/j.compeleceng.2016.04.005.
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Boschmann, Alexander, et al. “FPGA-Based Acceleration of High Density Myoelectric Signal Processing.”10.1109/reconfig.2015.7393312__2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2016, doi:10.1109/reconfig.2015.7393312.
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Cedric Mertens, Jan. Sprint Diagnostic with RTK-GPS \'26; IMU Sensor Fusion. Paderborn University, 2016.
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Nassery, Abdul Sami. Implementation of Bilinear Pairings on Reconfigurable Hardware. Paderborn University, 2016.
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Amin, Omair. Acceleration of EMTP for Distribution Networks on Data Flow Machines Using the Latency Insertion Method. Paderborn University, 2016.
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Anwer, Jahanzeb, and Marco Platzner. “Boolean Difference Based Reliability Evaluation of Fault Tolerant Circuit Structures on FPGAs.”10.1109/DSD.2016.35__Euromicro Conference on Digital System Design (DSD), 2016, doi:10.1109/DSD.2016.35.
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Boschmann, Alexander, et al. “A Novel Immersive Augmented Reality System for Prosthesis Training and Assessment.” Proc. IEEE Int. Conf. Biomed. Health Informatics (BHI), 2016.
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Graf, Tobias, and Marco Platzner. “Adaptive Playouts for Online Learning of Policies during Monte Carlo Tree Search.”10.1016/j.tcs.2016.06.029__Journal Theoretical Computer Science, vol. 644, Elsevier, 2016, pp. 53–62, doi:10.1016/j.tcs.2016.06.029.
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Horstmann, Jens. Beschleunigte Simulation Elektrischer Stromnetze Mit GPUs. Paderborn University, 2016.
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Ma, Chenjie, et al. “Optimal Generation Dispatch of Distributed Generators Considering Fair Contribution to Grid Voltage Control.”10.1016/j.renene.2015.07.083__Renewable Energy, vol. 87, no. (part 2), Elsevier, 2016, pp. 946–53, doi:10.1016/j.renene.2015.07.083.
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Makeswaran, Vignesh. Operating System Support for Reconfigurable Cache. Paderborn University, 2016.
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Ibne Ashraf, Ishraq. Private/Shared Data Classification and Implementation for a Multi-Softcore Platform. Paderborn University, 2016.
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Meisner, Sebastian, and Marco Platzner. “Thread Shadowing: On the Effectiveness of Error Detection at the Hardware Thread Level.”10.1109/ReConFig.2016.7857193__Reconfigurable Computing and FPGAs (ReConFig), 2016 International Conference On, 2016, pp. 1–8, doi:10.1109/ReConFig.2016.7857193.
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Schmidt, Marco. Konzeption Und Implementierung Einer Digitalen Ansteuerung Für Den Betrieb Einer Elektrischen Sendereinheit Für Induktive Energieübertragung. Paderborn University, 2016.
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Squillero, Giovanni, et al. Applications of Evolutionary Computation - 19th European Conference, EvoApplications. Vol. 9597, Springer, 2016.
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Ghribi, Ines, et al. “RCo-Design: New Visual Environment for Reconfigurable Embedded Systems.” Proceedings of the 30th European Simulation and Modelling Conference (ESM), 2016.
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Ghribi, Ines, et al. “New Co-Design Methodology for Real-Time Embedded Systems.” Proceedings of the 11th International Conference on Software Engineering and Applications (ICSOFT-EA), 2016, pp. 185–95.
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Ghasemzadeh Mohammadi, Hassan, et al. “Efficient Statistical Parameter Selection for Nonlinear Modeling of Process/Performance Variation.”10.1109/TCAD.2016.2547908__IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. PP, no. 99, IEEE, 2016, pp. 1–1, doi:10.1109/TCAD.2016.2547908.
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Hermansen, Sven. Custom Memory Controller for ReconOS. Paderborn University, 2016.
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Lewis, Peter R., et al., editors. Self-Aware Computing Systems: An Engineering Approach. Springer, 2016, doi:10.1007/978-3-319-39675-0.
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Boschmann, Alexander, et al. “FPGA-Based Acceleration of High Density Myoelectric Signal Processing.”10.1109/reconfig.2015.7393312__2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2016, doi:10.1109/reconfig.2015.7393312.
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DOI: 10.1109/reconfig.2015.7393312

Graf, Tobias, and Marco Platzner. “Using Deep Convolutional Neural Networks in Monte Carlo Tree Search.” Computer and Games, 2016.
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Graf, Tobias, and Marco Platzner. “Monte-Carlo Simulation Balancing Revisited.” IEEE Computational Intelligence and Games, 2016.
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Wiersema, Tobias, and Marco Platzner. “Verifying Worst-Case Completion Times for Reconfigurable Hardware Modules Using Proof-Carrying Hardware.”10.1109/ReCoSoC.2016.7533910__Proceedings of the 11th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC 2016), 2016, pp. 1--8, doi:10.1109/ReCoSoC.2016.7533910.
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Agne, Andreas, et al. “ReconOS.”10.1007/978-3-319-26408-0_13__FPGAs for Software Programmers, edited by Dirk Koch et al., Springer International Publishing, 2016, pp. 227–44, doi:10.1007/978-3-319-26408-0_13.
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Agne, Andreas, et al. “Self-Aware Compute Nodes.”10.1007/978-3-319-39675-0_8__Self-Aware Computing Systems, Springer International Publishing, 2016, pp. 145–65, doi:10.1007/978-3-319-39675-0_8.
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Lösch, Achim, et al. “Performance-Centric Scheduling with Task Migration for a Heterogeneous Compute Node in the Data Center.” Proceedings of the 2016 Design, Automation &; Test in Europe Conference &; Exhibition (DATE), EDA Consortium / IEEE, 2016, pp. 912–17.
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Wiersema, Tobias, et al. “On-The-Fly Verification of Reconfigurable Image Processing Modules Based on a Proof-Carrying Hardware Approach.”10.1007/978-3-319-16214-0_32__Proceedings of the International Symposium in Reconfigurable Computing (ARC), 2015, pp. 365--372, doi:10.1007/978-3-319-16214-0_32.
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Knorr, Christoph. Evaluation von Bildverarbeitungsalgorithmen in heterogenen Rechenknoten. Universität Paderborn, 2015.
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Torresen, Jim, et al. “Self-Aware and Self-Expressive Systems – Guest Editor’s Introduction.”10.1109/MC.2015.205__IEEE Computer, vol. 48, no. 7, IEEE Computer Society, 2015, pp. 18–20, doi:10.1109/MC.2015.205.
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DOI: 10.1109/MC.2015.205

Ahmed, Abdullah Fathi. Self-Optimizing Organic Cache. Paderborn University, 2015.
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Beisel, Tobias. Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing. Logos Verlag Berlin GmbH, 2015.
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Hangmann, Hendrik. Evolution of Heat Flow Prediction Models for FPGA Devices. Paderborn University, 2015.
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Haupt, Christian. Computer Vision Basierte Klassifikation von HD EMG Signalen. Paderborn University, 2015.
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Ho, Nam, et al. “Microarchitectural Optimization by Means of Reconfigurable and Evolvable Cache Mappings.”10.1109/AHS.2015.7231178__Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS), 2015, pp. 1–7, doi:10.1109/AHS.2015.7231178.
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Kaufmann, Paul, and Cong Shen. “Generator Start-up Sequences Optimization for Network Restoration Using Genetic Algorithm and Simulated Annealing.” Genetic and Evolutionary Computation (GECCO), ACM, 2015, pp. 409–16.
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Meisner, Sebastian, and Marco Platzner. “Comparison of Thread Signatures for Error Detection in Hybrid Multi-Cores.”10.1109/FPT.2015.7393153__Field Programmable Technology (FPT), 2015 International Conference On, 2015, pp. 212–15, doi:10.1109/FPT.2015.7393153.
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Meißner, Roland. Konzept Und Implementation Einer Benutzeroberfläche Zur Generierung Virtueller FPGAs. Universität Paderborn, 2015.
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