J. Anwer and M. Platzner, “Boolean Difference Based Reliability Evaluation of Fault Tolerant Circuit Structures on FPGAs,” in Euromicro Conference on Digital System Design (DSD), 2016.

A. Boschmann, S. Dosen, A. Werner, A. Raies, and D. Farina, “A novel immersive augmented reality system for prosthesis training and assessment,” in Proc. IEEE Int. Conf. Biomed. Health Informatics (BHI), 2016.

T. Graf and M. Platzner, “Adaptive playouts for online learning of policies during Monte Carlo Tree Search,” Journal Theoretical Computer Science, vol. 644, pp. 53–62, 2016.

J. Horstmann, Beschleunigte Simulation elektrischer Stromnetze mit GPUs. Paderborn University, 2016.

C. Ma, P. Kaufmann, J.-C. Töbermann, and M. Braun, “Optimal Generation Dispatch of Distributed Generators Considering Fair Contribution to Grid Voltage Control,” Renewable Energy, vol. 87, no. (part 2), pp. 946–953, 2016.

V. Makeswaran, Operating System Support for Reconfigurable Cache. Paderborn University, 2016.

I. Ibne Ashraf, Private/Shared Data Classification and Implementation for a Multi-Softcore Platform. Paderborn University, 2016.

S. Meisner and M. Platzner, “Thread Shadowing: On the Effectiveness of Error Detection at the Hardware Thread Level,” in Reconfigurable Computing and FPGAs (ReConFig), 2016 International Conference on, 2016, pp. 1–8.

M. Schmidt, Konzeption und Implementierung einer digitalen Ansteuerung für den Betrieb einer elektrischen Sendereinheit für induktive Energieübertragung. Paderborn University, 2016.

G. Squillero et al., Applications of Evolutionary Computation - 19th European Conference, EvoApplications, vol. 9597. Springer, 2016.

I. Ghribi, R. Ben Abdallah, M. Khalgui, and M. Platzner, “RCo-Design: New Visual Environment for Reconfigurable Embedded Systems,” in Proceedings of the 30th European Simulation and Modelling Conference (ESM), 2016.

I. Ghribi, R. Ben Abdallah, M. Khalgui, and M. Platzner, “New Co-design Methodology for Real-time Embedded Systems,” in Proceedings of the 11th International Conference on Software Engineering and Applications (ICSOFT-EA), 2016, pp. 185–195.

H. Ghasemzadeh Mohammadi, P.-E. Gaillardon, and G. De Micheli, “Efficient Statistical Parameter Selection for Nonlinear Modeling of Process/Performance Variation,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. PP, no. 99, pp. 1–1, 2016.

S. Hermansen, Custom Memory Controller for ReconOS. Paderborn University, 2016.

P. R. Lewis, M. Platzner, B. Rinner, J. Tørresen, and X. Yao, Eds., Self-aware Computing Systems: An Engineering Approach. Cham: Springer, 2016.

A. Boschmann, A. Agne, L. M. Witschen, G. Thombansen, F. Kraus, and M. Platzner, “FPGA-based acceleration of high density myoelectric signal processing,” in 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig), Mexiko City, Mexiko, 2016.

T. Graf and M. Platzner, “Using Deep Convolutional Neural Networks in Monte Carlo Tree Search,” in Computer and Games, 2016.

T. Graf and M. Platzner, “Monte-Carlo Simulation Balancing Revisited,” in IEEE Computational Intelligence and Games, 2016.

T. Wiersema and M. Platzner, “Verifying Worst-Case Completion Times for Reconfigurable Hardware Modules using Proof-Carrying Hardware,” in Proceedings of the 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2016), 2016, pp. 1--8.

A. Agne, M. Platzner, C. Plessl, M. Happe, and E. Lübbers, “ReconOS,” in FPGAs for Software Programmers, D. Koch, F. Hannig, and D. Ziener, Eds. Cham: Springer International Publishing, 2016, pp. 227–244.

A. Agne, M. Happe, A. Lösch, C. Plessl, and M. Platzner, “Self-aware Compute Nodes,” in Self-aware Computing Systems, Cham: Springer International Publishing, 2016, pp. 145–165.

A. Lösch, T. Beisel, T. Kenter, C. Plessl, and M. Platzner, “Performance-centric scheduling with task migration for a heterogeneous compute node in the data center,” in Proceedings of the 2016 Design, Automation &; Test in Europe Conference &; Exhibition (DATE), 2016, pp. 912–917.

T. Wiersema, S. Wu, and M. Platzner, “On-The-Fly Verification of Reconfigurable Image Processing Modules based on a Proof-Carrying Hardware Approach,” in Proceedings of the International Symposium in Reconfigurable Computing (ARC), 2015, pp. 365--372.

C. Knorr, Evaluation von Bildverarbeitungsalgorithmen in heterogenen Rechenknoten. Universität Paderborn, 2015.

J. Torresen, C. Plessl, and X. Yao, “Self-Aware and Self-Expressive Systems – Guest Editor’s Introduction,” IEEE Computer, vol. 48, no. 7, pp. 18–20, 2015.

A. F. Ahmed, Self-Optimizing Organic Cache. Paderborn University, 2015.

T. Beisel, Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing. Berlin: Logos Verlag Berlin GmbH, 2015.

H. Hangmann, Evolution of Heat Flow Prediction Models for FPGA Devices. Paderborn University, 2015.

C. Haupt, Computer Vision basierte Klassifikation von HD EMG Signalen. Paderborn University, 2015.

N. Ho, A. F. Ahmed, P. Kaufmann, and M. Platzner, “Microarchitectural optimization by means of reconfigurable and evolvable cache mappings,” in Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS), 2015, pp. 1–7.

P. Kaufmann and C. Shen, “Generator Start-up Sequences Optimization for Network Restoration Using Genetic Algorithm and Simulated Annealing,” in Genetic and Evolutionary Computation (GECCO), 2015, pp. 409–416.

S. Meisner and M. Platzner, “Comparison of thread signatures for error detection in hybrid multi-cores,” in Field Programmable Technology (FPT), 2015 International Conference on, 2015, pp. 212–215.

R. Meißner, Konzept und Implementation einer Benutzeroberfläche zur Generierung virtueller FPGAs. Universität Paderborn, 2015.

T. Posewsky, Acceleration of Artificial Neural Networks on a Zynq Platform. Paderborn University, 2015.

A. M. Mora et al., Applications of Evolutionary Computation - 18th European Conference, EvoApplications, vol. 9028. Copenhagen, Denmark: Springer, 2015.

P. H.W. Leong et al., “Significant papers from the first 25 years of the FPL conference,” in Proceedings of the 25th International Conference on Field Programmable Logic and Applications (FPL), 2015, pp. 1–3.

I. Ghribi, R. Ben Abdallah, M. Khalgui, and M. Platzner, “New Codesign Solutions for Modelling and Partitioning of Probabilistic Reconfigurable Embedded Software,” in Proceedings of the 29th European Simulation and Modelling Conference (ESM), 2015.

H. Ghasemzadeh Mohammadi, P.-E. Gaillardon, and G. De Micheli, “From Defect Analysis to Gate-Level Fault Modeling of Controllable-Polarity Silicon Nanowires,” IEEE Transactions on Nanotechnology, vol. 14, no. 6, pp. 1117–1126, 2015.

H. Ghasemzadeh Mohammadi, P.-E. Gaillardon, J. Zhang, G. De Micheli, E. Sanchez, and M. S. Reorda, “On the design of a fault tolerant ripple-carry adder with controllable-polarity transistors,” in 2015 IEEE Computer Society Annual Symposium on VLSI, 2015, pp. 491–496.

H. Ghasemzadeh Mohammadi, P.-E. Gaillardon, and G. De Micheli, “Fault modeling in controllable polarity silicon nanowire circuits,” in Proceedings of the 2015 Design, Automation &; Test in Europe Conference \'26; Exhibition, 2015, pp. 453–458.

Z. Guettatfi, O. Kermia, and A. Khouas, “Over effective hard real-time hardware tasks scheduling and allocation,” in 25th International Conference on Field Programmable Logic and Applications (FPL), 2015.

T. Graf and M. Platzner, “Adaptive Playouts in Monte-Carlo Tree Search with Policy-Gradient Reinforcement Learning,” in Advances in Computer Games: 14th International Conference, ACG 2015, Leiden, The Netherlands, July 1-3, 2015, Revised Selected Papers, 2015, pp. 1–11.

T. Kenter, H. Schmitz, and C. Plessl, “Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study,”10.1155/2015/859425__International Journal of Reconfigurable Computing (IJRC), vol. 2015, Art. no. 859425, 2015, doi:10.1155/2015/859425 .

M. Damschen and C. Plessl, “Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores,” 2015.

J. Schumacher et al., “Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm,”10.1145/2675743.2771824__2015, doi:10.1145/2675743.2771824 .

C. Plessl, M. Platzner, and P. J. Schreier, “Aktuelles Schlagwort: Approximate Computing,”10.1007/s00287-015-0911-z__Informatik Spektrum, no. 5, pp. 396–399, 2015, doi:10.1007/s00287-015-0911-z .

M. Damschen, H. Riebler, G. F. Vaz, and C. Plessl, “Transparent offloading of computational hotspots from binary code to Xeon Phi,”10.7873/DATE.2015.1124__in Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE), 2015, pp. 1078–1083, doi:10.7873/DATE.2015.1124 .

S. Meisner and M. Platzner, “Thread Shadowing: Using Dynamic Redundancy on Hybrid Multi-cores for Error Detection,” in Proceedings of the 10th International Symposium on Applied Reconfigurable Computing (ARC), 2014, pp. 283–290.

T. Graf, L. Schaefers, and M. Platzner, “On Semeai Detection in Monte-Carlo Go,” in Proc. Conf. on Computers and Games (CG), 2014, no. 8427, pp. 14–25.

T. Wiersema, S. Drzevitzky, and M. Platzner, “Memory Security in Reconfigurable Computers: Combining Formal Verification with Monitoring,” in Proceedings of the International Conference on Field-Programmable Technology (FPT), 2014, pp. 167–174.

M.-C. Jakobs, M. Platzner, T. Wiersema, and H. Wehrheim, “Integrating Software and Hardware Verification,” in Proceedings of the 11th International Conference on Integrated Formal Methods (iFM), 2014, pp. 307–322.

T. Wiersema, A. Bockhorn, and M. Platzner, “Embedding FPGA Overlays into Configurable Systems-on-Chip: ReconOS meets ZUMA,” in Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 2014, pp. 1–6.

L. Schaefers and M. Platzner, “A Novel Technique and its Application to Computer Go,” IEEE Transactions on Computational Intelligence and AI in Games, vol. 6, no. 3, pp. 361–374, 2014.

H. Giefers and M. Platzner, “An FPGA-based Reconfigurable Mesh Many-Core,” IEEE Transactions on Computers, vol. 63, no. 12, pp. 2919–2932, 2014.

J. Anwer, M. Platzner, and S. Meisner, “FPGA Redundancy Configurations: An Automated Design Space Exploration,” in Reconfigurable Architectures Workshop (RAW), 2014.

A. Bockhorn, Echtzeit Klassifikation von sEMG Signalen mit einem low-cost DSP Evaluation Board. Paderborn University, 2014.

A. Boschmann and M. Platzner, “A computer vision-based approach to high density EMG pattern recognition using structural similarity,” in Proc. MyoElectric Controls Symposium (MEC), 2014.

A. Boschmann and M. Platzner, “Towards robust HD EMG pattern recognition: Reducing electrode displacement effect using structural similarity,” in Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC), 2014.

M. Brand, A Generalized Loop Accelerator Implemented as a Coarse-Grained Array. Paderborn University, 2014.

M. Damschen, Easy-to-use-on-the-fly binary program acceleration on many-cores. Paderborn University, 2014.

K. Glette and P. Kaufmann, “Lookup Table Partial Reconfiguration for an Evolvable Hardware Classifier System,” in IEEE Congress on Evolutionary Computation (CEC), 2014.

C. Hagedorn, Entwicklung einer codegrößenoptimierten Softwarebibliothek für 8-Bit Mikrocontroller in netzunabhängigen Notleuchten. Paderborn University, 2014.

N. Ho, P. Kaufmann, and M. Platzner, “A hardware/software infrastructure for performance monitoring on LEON3 multicore platforms,” in 24th Intl. Conf. on Field Programmable Logic and Applications (FPL), 2014, pp. 1–4.

N. Ho, P. Kaufmann, and M. Platzner, “Towards self-adaptive caches: A run-time reconfigurable multi-core infrastructure,” in 2014 IEEE Intl. Conf. on Evolvable Systems (ICES), 2014, pp. 31–37.

F. König, EMG-basierte simultane und proportionale Online-Steuerung einer virtuellen Prothese. Paderborn University, 2014.

B. Koch, Hardware Acceleration of Mechatronic Controllers on a Zynq Platform FPGA. Paderborn University, 2014.

R. Mittendorf, Advanced AES-key recovery from decayed RAM using multi-threading and FPGAs. Paderborn University, 2014.

C. Rüthing, The Xilinx Zynq Architecture as a Platform for Reconfigurable Heterogeneous Multi-Cores. Paderborn University, 2014.

L. Schäfers, Parallel Monte-Carlo Tree Search for HPC Systems and its Application to Computer Go. Berlin: Logos Verlag Berlin GmbH, 2014.

C. Shen, P. Kaufmann, and M. Braun, “Optimizing the Generator Start-up Sequence After a Power System Blackout,” in IEEE Power and Energy Society General Meeting (IEEE GM), 2014.

C. Shen, P. Kaufmann, and M. Braun, “A New Distribution Network Reconfiguration and Restoration Path Selection Algorithm,” in Power Systems Computation Conference (PSCC), 2014.

S. Surmund, Multithreaded Parallelization of Mechatronic Controllers on a Zynq Platform FPGA. Paderborn University, 2014.

A. I. Esparcia-Alc\rquote azar et al., Applications of Evolutionary Computation - 17th European Conference, EvoApplications, vol. 8602. Granada, Spain: Springer, 2014.

J. Anwer and M. Platzner, “Analytic reliability evaluation for fault-tolerant circuit structures on FPGAs,” in IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2014, pp. 177–184.

H. Ghasemzadeh Mohammadi, P.-E. Gaillardon, M. Yazdani, and G. De Micheli, “Fast process variation analysis in nano-scaled technologies using column-wise sparse parameter selection,” in 2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), 2014, pp. 163–168.

T. Graf and M. Platzner, “Common Fate Graph Patterns in Monte Carlo Tree Search for Computer Go,” in 2014 IEEE Conference on Computational Intelligence and Games, 2014, pp. 1–8.

M. Platzner and C. Plessl, “Verschiebungen an der Grenze zwischen Hardware und Software,” in Logiken strukturbildender Prozesse: Automatismen, J. Künsemöller, N. O. Eke, L. Foit, and T. Kaerlein, Eds. Paderborn: Wilhelm Fink, 2014, pp. 123–144.

T. Kenter, G. F. Vaz, and C. Plessl, “Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer,”10.1007/978-3-319-05960-0_13__in Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC), 2014, vol. 8405, pp. 144–155, doi:10.1007/978-3-319-05960-0_13 .

A. Agne, H. Hangmann, M. Happe, M. Platzner, and C. Plessl, “Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators,”10.1016/j.micpro.2013.12.001__Microprocessors and Microsystems, vol. 38, no. 8, Part B, pp. 911–919, 2014, doi:10.1016/j.micpro.2013.12.001 .

H. Riebler, T. Kenter, C. Plessl, and C. Sorge, “Reconstructing AES Key Schedules from Decayed Memory with FPGAs,”10.1109/FCCM.2014.67__in Proceedings of Field-Programmable Custom Computing Machines (FCCM), 2014, pp. 222–229, doi:10.1109/FCCM.2014.67 .

A. Agne, M. Happe, A. Lösch, C. Plessl, and M. Platzner, “Self-awareness as a Model for Designing and Operating Heterogeneous Multicores,”10.1145/2617596__ACM Transactions on Reconfigurable Technology and Systems (TRETS), vol. 7, no. 2, Art. no. 13, 2014, doi:10.1145/2617596 .

A. Agne et al., “ReconOS - An Operating System Approach for Reconfigurable Computing,”10.1109/MM.2013.110__IEEE Micro, vol. 34, no. 1, pp. 60–71, 2014, doi:10.1109/MM.2013.110 .

G. C. Durelli et al., “Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach,”10.1109/ISPA.2014.27__in Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA), 2014, pp. 142–149, doi:10.1109/ISPA.2014.27 .

G. F. Vaz, H. Riebler, T. Kenter, and C. Plessl, “Deferring Accelerator Offloading Decisions to Application Runtime,”10.1109/ReConFig.2014.7032509__in Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 2014, pp. 1–8, doi:10.1109/ReConFig.2014.7032509 .

T. Kenter, H. Schmitz, and C. Plessl, “Kernel-Centric Acceleration of High Accuracy Stereo-Matching,”10.1109/ReConFig.2014.7032535__in Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 2014, pp. 1–8, doi:10.1109/ReConFig.2014.7032535 .

G. C. Durelli et al., “SAVE: Towards efficient resource management in heterogeneous system architectures,”10.1007/978-3-319-05960-0_38__2014, doi:10.1007/978-3-319-05960-0_38 .

H. Giefers, C. Plessl, and J. Förstner, “Accelerating Finite Difference Time Domain Simulations with Reconfigurable Dataflow Computers,”10.1145/2641361.2641372__ACM SIGARCH Computer Architecture News, vol. 41, no. 5, pp. 65–70, 2014, doi:10.1145/2641361.2641372 .

P. Kaufmann, Adapting Hardware Systems by Means of Multi-Objective Evolution. Berlin: Logos Verlag Berlin GmbH, 2013.

S. Kasap and S. Redif, “FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm,” in Proc. IEEE Signal Processing and Communications Conf. (SUI), 2013.

S. Kasap and S. Redif, “Novel Field-Programmable Gate Array Architecture for Computing the Eigenvalue Decomposition of Para-Hermitian Polynomial Matrices,” IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 22, no. 3, pp. 522–536, 2013.

M. Happe, Performance and thermal management on self-adaptive hybrid multi-cores. Berlin: Logos Verlag Berlin GmbH, 2013.

M. Happe, E. Lübbers, and M. Platzner, “A Self-adaptive Heterogeneous Multi-core Architecture for Embedded Real-time Video Object Tracking,” International Journal of Real-time Image Processing, vol. 8, no. 1, pp. 95–110, 2013.

J. Anwer, S. Meisner, and M. Platzner, “Dynamic reliability management: Reconfiguring reliability-levels of hardware designs at runtime,” in Reconfigurable Computing and FPGAs (ReConFig), 2013 International Conference on, 2013, pp. 1–6.

C. Bick, Beschleunigung von Tiefenberechnung aus Stereobildern durch FPGA-basierte Datenflussrechner. Paderborn University, 2013.

A. Boschmann, B. Nofen, and M. Platzner, “Improving transient state myoelectric signal recognition in hand movement classification using gyroscopes,” in Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC), 2013.

A. Boschmann and M. Platzner, “Reducing the limb position effect in pattern recognition based myoelectric control using a high density electrode array,” in Proc. IEEE ISSNIP Biosignals and Biorobotics Conference (BRC), 2013.

K. Glette, P. Kaufmann, C. Assad, and M. Wolf, “Investigating Evolvable Hardware Classification for the BioSleeve Electromyographic Interface,” in IEEE Intl. Conf. on Evolvable Systems (ICES), 2013, vol. 1, pp. 1–1.

P. Kaufmann, Adapting Hardware Systems by Means of Multi-Objective Evolution. Berlin: Logos Verlag, 2013.

P. Kaufmann, K. Glette, T. Gruber, M. Platzner, J. Torresen, and B. Sick, “Classification of Electromyographic Signals: Comparing Evolvable Hardware to Conventional Classifiers,” IEEE Transactions on Evolutionary Computation, vol. 17, no. 1, pp. 46–63, 2013.

M. Knoop, Behavior Models for Electric Vehicles. IWES Kassel, 2013.