Danne, K., &; Platzner, M. (2006). Partitioned Scheduling of Periodic Real-time Tasks onto Reconfigurable Hardware. In Proceedings of the 13th Reconfigurable Architectures Workshop (RAW). IEEE CS Press.

Plessl, C., &; Platzner, M. (2005). Zippy – A coarse-grained reconfigurable array with support for hardware virtualization. In Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP) (pp. 213–218). IEEE Computer Society.https://doi.org/10.1109/ASAP.2005.69 

Enzler, R., Plessl, C., &; Platzner, M. (2005). System-level performance evaluation of reconfigurable processors. Microprocessors and Microsystems, 29(2–3), 63–73.https://doi.org/10.1016/j.micpro.2004.06.004 

Danne, K., &; Platzner, M. (2005). Periodic real-time scheduling for FPGA computers. In Proceedings of the Third International Workshop on Intelligent Solutions in Embedded Systems (WISES).https://doi.org/10.1109/wises.2005.1438720 

Danne, K., &; Platzner, M. (2005). Memory-demanding Periodic Real-time Applications on FPGA Computers. In Work-in-Progress Proceedings of the 17th Euromicro Conference on Real-time Systems (ECRTS).

Danne, K., &; Platzner, M. (2005). A heuristic approach to schedule periodic real-time tasks on reconfigurable hardware. In Proceedings of the 15th International Conference on Field Programmable Logic and Applications (FPL). IEEE CS Press.https://doi.org/10.1109/fpl.2005.1515787 

Plessl, C., &; Platzner, M. (2004). Virtualization of Hardware – Introduction and Survey. In Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) (pp. 63–69). CSREA Press.

Steiger, C., Walder, H., &; Platzner, M. (2004). Operating systems for reconfigurable embedded platforms: online scheduling of real-time tasks. IEEE Transactions on Computers, 53(11), 1393–1407.https://doi.org/10.1109/tc.2004.99 

Walder, H., &; Platzner, M. (2004). A Runtime Environment for Reconfigurable Hardware Operating Systems. In Proceedings of the 14th International Conference on Field Programmable Logic and Applications (FPL) (pp. 831–835). Berlin, Heidelberg: Springer.https://doi.org/10.1007/978-3-540-30117-2_84 

Walder, H., Nobs, S., &; Platzner, M. (2004). XF-BOARD: A Prototyping Platform for Reconfigurable Hardware Operating Systems. In Proceedings of the 4th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press.

Dyer, M., Platzner, M., &; Thiele, L. (2004). Efficient Execution of Process Networks on a Reconfigurable Hardware Virtual Machine. In Proceedings 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM). IEEE CS Press.https://doi.org/10.1109/fccm.2004.31 

Plessl, C., &; Platzner, M. (2003). TKDM – A Reconfigurable Co-processor in a PC’s Memory Slot. In Proc. Int. Conf. on Field Programmable Technology (ICFPT) (pp. 252–259). IEEE Computer Society.https://doi.org/10.1109/FPT.2003.1275755 

Plessl, C., Enzler, R., Walder, H., Beutel, J., Platzner, M., Thiele, L., &; Tröster, G. (2003). The Case for Reconfigurable Hardware in Wearable Computing. Personal and Ubiquitous Computing, 7(5), 299–308.https://doi.org/10.1007/s00779-003-0243-x 

Plessl, C., &; Platzner, M. (2003). Instance-Specific Accelerators for Minimum Covering. Journal of Supercomputing, 26(2), 109–129.https://doi.org/10.1023/a:1024443416592 

Enzler, R., Plessl, C., &; Platzner, M. (2003). Virtualizing Hardware with Multi-Context Reconfigurable Arrays. In Proc. Int. Conf. on Field Programmable Logic and Applications (FPL) (Vol. 2778, pp. 151–160). Springer.https://doi.org/10.1007/b12007 

Enzler, R., Plessl, C., &; Platzner, M. (2003). Co-simulation of a Hybrid Multi-Context Architecture. In Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) (pp. 174–180). CSREA Press.

Walder, H., &; Platzner, M. (2003). Online scheduling for block-partitioned reconfigurable devices. In Proceedings Design, Automation and Test in Europe Conference (DATE) (pp. 290–295). IEEE CS Press.https://doi.org/10.1109/date.2003.1253622 

Walder, H., Steiger, C., &; Platzner, M. (2003). Fast online task placement on FPGAs: free space partitioning and 2D-hashing. In Proceedings International Parallel and Distributed Processing Symposium. IEEE CS Press.https://doi.org/10.1109/ipdps.2003.1213329 

Walder, H., &; Platzner, M. (2003). Reconfigurable Hardware Operating Systems: From Design Concepts to Realizations. In Proceedings of the 3rd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA) (pp. 284–287). CSREA Press.

Steiger, C., Walder, H., &; Platzner, M. (2003). Heuristics for Online Scheduling Real-Time Tasks to Partially Reconfigurable Devices. In Proceedings of the 13th International Conference on Field Programmable Logic and Applications (FPL) (pp. 575–584). Berlin, Heidelberg: Springer.https://doi.org/10.1007/978-3-540-45234-8_56 

Steiger, C., Walder, H., Platzner, M., &; Thiele, L. (2003). Online scheduling and placement of real-time tasks to partially reconfigurable devices. In Proceedings 24th IEEE International Real-Time Systems Symposium (RTSS) (pp. 252–235). IEEE CS Press.https://doi.org/10.1109/real.2003.1253269 

Plessl, C., Enzler, R., Walder, H., Beutel, J., Platzner, M., &; Thiele, L. (2002). Reconfigurable Hardware in Wearable Computing Nodes. In Proc. Int. Symp. on Wearable Computers (ISWC) (pp. 215–222). IEEE Computer Society.https://doi.org/10.1109/ISWC.2002.1167250 

Dyer, M., Plessl, C., &; Platzner, M. (2002). Partially Reconfigurable Cores for Xilinx Virtex. In Proc. Int. Conf. on Field Programmable Logic and Applications (FPL) (Vol. 2438, pp. 292–301). Springer.https://doi.org/10.1007/3-540-46117-5 

Plessl, C., &; Platzner, M. (2002). Custom Computing Machines for the Set Covering Problem. In Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM) (pp. 163–172). IEEE Computer Society.https://doi.org/10.1109/FPGA.2002.1106671 

Eisenring, M., &; Platzner, M. (2002). A Framework for Run-time Reconfigurable Systems. The Journal of Supercomputing, 21(2), 145–159.https://doi.org/10.1023/a:1013627403946 

Walder, H., &; Platzner, M. (2002). Non-preemptive Multitasking on FPGAs: Task Placement and Footprint Transform. In Proceedings of the 2nd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA) (pp. 24–30). CSREA Press.

Plessl, C., &; Platzner, M. (2001). Instance-Specific Accelerators for Minimum Covering. In Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) (pp. 85–91). CSREA Press.

Enzler, R., Platzner, M., Plessl, C., Thiele, L., &; Tröster, G. (2001). Reconfigurable Processors for Handhelds and Wearables: Application Analysis. In Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III (Vol. 4525, pp. 135–146).https://doi.org/10.1117/12.434376 

Mencer, O., Platzner, M., Morf, M., &; J. Flynn, M. (2001). Object-oriented domain specific compilers for programming FPGAs. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 9(1), 205–210.https://doi.org/10.1109/92.920835 

Enzler, R., &; Platzner, M. (2001). Dynamically Reconfigurable Processors. TELEMATIK, Zeitschrift des Telematik-Ingebieur-Verbandes 7(1).

Platzner, M. (2000). Reconfigurable accelerators for combinatorial problems. Computer, 33(4), 58–60.https://doi.org/10.1109/2.839322 

Eisenring, M., &; Platzner, M. (2000). Synthesis of Interfaces and Communication in Reconfigurable Embedded Systems. IEE Proceedings -- Computers &; Digital Techniques, 147, 159–165.https://doi.org/10.1049/ip-cdt:20000496 

Platzner, M., Rinner, B., &; Weiss, R. (2000). Toward embedded qualitative simulation: a specialized computer architecture for QSim. IEEE Intelligent Systems, 15(2), 62–68.https://doi.org/10.1109/5254.850829 

Eisenring, M. H., &; Platzner, M. (2000). An Implementation Framework for Run-time Reconfigurable Systems. In Proceedings of the 2nd International Workshop on Engineering of Reconfigurable Hardware/Software Objects (ENREGLE) (pp. 151–157). CSREA Press.

Eisenring, M., &; Platzner, M. (2000). Optimization of Run-time Reconfigurable Embedded Systems. In Proceedings of the 10th International Workshop on Field Programmable Logic and Applications (FPL) (pp. 565–574). Springer.

Mencer, O., &; Platzner, M. (1999). Dynamic circuit generation for Boolean satisfiability in an object-oriented design environment. In Proceedings of the 32nd Annual Hawaii International Conference on Systems Sciences (HICSS-32). IEEE CS Press.https://doi.org/10.1109/hicss.1999.772883 

Eisenring, M., Platzner, M., &; Thiele, L. (1999). Communication Synthesis for Reconfigurable Embedded Systems. In Proceedings of the 9th International Workshop on Field Programmable Logic and Applications (FPL) (Vol. 1673, pp. 205–214). Springer.https://doi.org/10.1007/978-3-540-48302-1_21 

Platzner, M. (1998). Reconfigurable Computer Architectures. E&;i Elektrotechnik Und Informationstechnik, 115, 143–148.

Platzner, M., &; Rinner, B. (1998). Design and Implementation of a Parallel Constraint Satisfaction Algorithm. International Journal of Computers &; Their Applications, 5, 106–116.

Platzner, M., Rinner, B., &; Weiss, R. (1998). A Distributed Computer Architecture for Fast Qualitative Simulation  (pp. 106–107). Texas Instruments, The Elite Yearbook 1997 - Digital Signal Processing Solutions from Europe’s leading Universities.

Platzner, M., &; De Micheli, G. (1998). Acceleration of satisfiability algorithms by reconfigurable hardware. In Proceedings of the 8th International Workshop on Field Programmable Logic and Applications (FPL)  (pp. 69–78). Berlin, Heidelberg: Springer .https://doi.org/10.1007/bfb0055234 

Platzner, M., Rinner, B., &; Weiss, R. (1997). A Computer Architecture to Support Qualitative Simulation in Industrial Applications. E &; i Elektrotechnik Und Informationstechnik, 114, 13–18.

Platzner, M., Rinner, B., &; Weiss, R. (1997). Parallel qualitative simulation. Simulation Practice and Theory, 5(7–8), 623–638.https://doi.org/10.1016/s0928-4869(97)00008-6 

Platzner, M., &; Peters, L. (1997). Fast Signature Segmentation on a Multi-DSP Architecture. In Proceedings of the SPIE: Conference on Parallel and Distributed Methods for Image Processing (Vol. 3166).

Röwekamp, T., Platzner, M., &; Peters, L. (1997). Specialized Architectures for Optical Flow Computation: A Performance Comparison of ASIC, DSP, and Multi-DSP. In Proceedings of the 8th International Conference on Signal Processing Applications &; Technology (ICSPAT) (pp. 829–833).

Lind, E., Platzner, M., &; Rinner, B. (1996). A Multi-DSP System with Dynamically Reconfigurable Processors. In Proceedings of the 7th International Conference on Signal Processing Applications &; Technology (ICSPAT).

Platzner, M., Rinner, B., &; Weiss, R. (1995). Exploiting Parallelism in Constraint Satisfaction for Qualitative Simulation. J.UCS Journal of Universal Computer Science, 12, 811–820.

Platzner, M., Rinner, B., &; Weiss, R. (1995). A Distributed Computer Architecture for Qualitative Simulation based on a Multi-DSP and FPGAs. In Proceedings of the 3rd Euromicro Workshop on Parallel and Distributed Processing  (pp. 311–318). IEEE CS Press.

Brenner, E., Ginthör-Kalcsics, R., Hranitzky, R., Platzner, M., Rinner, B., Steger, C., &; Weiss, R. (1995). High-Performance Simulators Based on Multi-TM0. In Proceedings of the 5th Annual Texas Instruments TM0 Educators Conference.

Friedl, G., Platzner, M., &; Rinner, B. (1995). A Special-Purpose Coprocessor for Qualitative Simulation. In Proceedings of the EURO-PAR’95 International Conference on Parallel Processing (pp. 695–698). Springer International Publishing.

Platzner, M., Rinner, B., &; Weiss, R. (1995). Parallel Qualitative Simulation. In Proceedings of the EUROSIM Congress (pp. 231–236). Elsevier.

Platzner, M., &; Rinner, B. (1995). Improving Performance of the Qualitative Simulator QSIM - Design and Implementation of a Specialized Computer Architecture. In Proceedings of the PDCS International Conference on Parallel and Distributed Computing Systems (pp. 494–501). ISCA.

Platzner, M., &; Rinner, B. (1995). High-Performance Qualitative Simulation on a Multi-DSP Architecture. In Proceedings of the 6th International Conference on Signal Processing Applications &; Technology (ICSPAT).

Hranitzky, R., &; Platzner, M. (1995). Design and Implementation of Adaptive Digital Filters on a Multi-TM0 System. In Proceedings of the 6th International Conference on Signal Processing Applications &; Technology (ICSPAT).

Platzner, M., Steger, C., &; Weiss, R. (1994). Experimental Evaluation of Multi-DSP Architectures in High Performance Applications. In Proceedings of the 7th Mediterranean Electrotechnical Conference. IEEE Press.

Platzner, M., &; Steger, C. (1993). Erfahrungen mit einer Multi-Signalprozessorarchitektur (TM0). Mikroelektronik.

Platzner, M., Steger, C., &; Weiss, R. (1993). Performance Measurements on a Multi-DSP Architecture with TM0. In Proceedings of the 4th International Conference on Signal Processing Applications &; Technology (ICSPAT). DSP Associates.

Ginthör, R., Platzner, M., &; Weiss, R. (1992). Experimental Results to Interprocessor Communication in Distributed Transputer-Systems. In Proceedings of the 1st Austrian-Hungarian Workshop on Transputer Applications (pp. 45–54).