Agne A, Happe M, Lösch A, Plessl C, Platzner M. Self-aware Compute Nodes. In: Self-Aware Computing Systems. Natural Computing Series (NCS). Springer International Publishing; 2016:145-165. doi:10.1007/978-3-319-39675-0_8
LibreCat: /record/156
DOI: 10.1007/978-3-319-39675-0_8

Lösch A, Beisel T, Kenter T, Plessl C, Platzner M. Performance-centric scheduling with task migration for a heterogeneous compute node in the data center. In: Proceedings of the 2016 Design, Automation &; Test in Europe Conference &; Exhibition (DATE). EDA Consortium / IEEE; 2016:912-917.
LibreCat: /record/168

Wiersema T, Wu S, Platzner M. On-The-Fly Verification of Reconfigurable Image Processing Modules based on a Proof-Carrying Hardware Approach. In: Proceedings of the International Symposium in Reconfigurable Computing (ARC). LNCS. ; 2015:365--372. doi:10.1007/978-3-319-16214-0_32
LibreCat: /record/269
DOI: 10.1007/978-3-319-16214-0_32

Knorr C. Evaluation von Bildverarbeitungsalgorithmen in heterogenen Rechenknoten. Universität Paderborn; 2015.
LibreCat: /record/3364

Torresen J, Plessl C, Yao X. Self-Aware and Self-Expressive Systems – Guest Editor’s Introduction. IEEE Computer. 2015;48(7):18-20. doi:10.1109/MC.2015.205
LibreCat: /record/1772
DOI: 10.1109/MC.2015.205

Ahmed AF. Self-Optimizing Organic Cache. Paderborn University; 2015.
LibreCat: /record/10615

Beisel T. Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing. Berlin: Logos Verlag Berlin GmbH; 2015.
LibreCat: /record/10624

Hangmann H. Evolution of Heat Flow Prediction Models for FPGA Devices. Paderborn University; 2015.
LibreCat: /record/10668

Haupt C. Computer Vision Basierte Klassifikation von HD EMG Signalen. Paderborn University; 2015.
LibreCat: /record/10671

Ho N, Ahmed AF, Kaufmann P, Platzner M. Microarchitectural optimization by means of reconfigurable and evolvable cache mappings. In: Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS). ; 2015:1-7. doi:10.1109/AHS.2015.7231178
LibreCat: /record/10673
DOI: 10.1109/AHS.2015.7231178

Kaufmann P, Shen C. Generator Start-up Sequences Optimization for Network Restoration Using Genetic Algorithm and Simulated Annealing. In: Genetic and Evolutionary Computation (GECCO). ACM; 2015:409-416.
LibreCat: /record/10693

Meisner S, Platzner M. Comparison of thread signatures for error detection in hybrid multi-cores. In: Field Programmable Technology (FPT), 2015 International Conference On. FPT. ; 2015:212-215. doi:10.1109/FPT.2015.7393153
LibreCat: /record/10711
DOI: 10.1109/FPT.2015.7393153

Meißner R. Konzept Und Implementation Einer Benutzeroberfläche Zur Generierung Virtueller FPGAs. Universität Paderborn; 2015.
LibreCat: /record/10714

Posewsky T. Acceleration of Artificial Neural Networks on a Zynq Platform. Paderborn University; 2015.
LibreCat: /record/10726

M. Mora A, Squillero G, Agapitos A, et al. Applications of Evolutionary Computation - 18th European Conference, EvoApplications. Vol 9028. Copenhagen, Denmark: Springer; 2015.
LibreCat: /record/10757

H.W. Leong P, Amano H, Anderson J, et al. Significant papers from the first 25 years of the FPL conference. In: Proceedings of the 25th International Conference on Field Programmable Logic and Applications (FPL). Imperial College; 2015:1-3. doi:10.1109/FPL.2015.7293747
LibreCat: /record/10765
DOI: 10.1109/FPL.2015.7293747

Ghribi I, Ben Abdallah R, Khalgui M, Platzner M. New Codesign Solutions for Modelling and Partitioning of Probabilistic Reconfigurable Embedded Software. In: Proceedings of the 29th European Simulation and Modelling Conference (ESM). ; 2015.
LibreCat: /record/10767

Ghasemzadeh Mohammadi H, Gaillardon P-E, De Micheli G. From Defect Analysis to Gate-Level Fault Modeling of Controllable-Polarity Silicon Nanowires. IEEE Transactions on Nanotechnology. 2015;14(6):1117-1126. doi:10.1109/TNANO.2015.2482359
LibreCat: /record/10770
DOI: 10.1109/TNANO.2015.2482359

Ghasemzadeh Mohammadi H, Gaillardon P-E, Zhang J, De Micheli G, Sanchez E, Reorda MS. On the design of a fault tolerant ripple-carry adder with controllable-polarity transistors. In: 2015 IEEE Computer Society Annual Symposium on VLSI. IEEE; 2015:491-496. doi:10.1109/ISVLSI.2015.13
LibreCat: /record/10771
DOI: 10.1109/ISVLSI.2015.13

Ghasemzadeh Mohammadi H, Gaillardon P-E, De Micheli G. Fault modeling in controllable polarity silicon nanowire circuits. In: Proceedings of the 2015 Design, Automation &; Test in Europe Conference \'26; Exhibition. EDA Consortium; 2015:453-458. doi:10.7873/DATE.2015.0428
LibreCat: /record/10772
DOI: 10.7873/DATE.2015.0428