Sekanina, L., Walker, J. A., Kaufmann, P., Plessl, C., &; Platzner, M. (2011). Evolution of Electronic Circuits. In Cartesian Genetic Programming (pp. 125–179). Springer Berlin Heidelberg.

Walker, J. A., Miller, J. F., Kaufmann, P., &; Platzner, M. (2011). Problem Decomposition in Cartesian Genetic Programming. In Cartesian Genetic Programming (pp. 35–99). Springer Berlin Heidelberg.

Welp, D. (2011). User Space Scheduling for Heterogeneous Systems. Paderborn University.

Agne, A., Platzner, M., &; Lübbers, E. (2011). Memory Virtualization for Multithreaded Reconfigurable Hardware. In Proceedings of the International Conference on Field Programmable Logic and Applications (FPL) (pp. 185–188). IEEE.https://doi.org/10.1109/fpl.2011.42 

Henkel, J., Hedrich, L., Herkersdorf, A., Kapitza, R., Lohmann, D., Marwedel, P.,https://doi.org/10.1145/2039370.2039384__Härtig, H. (2011). Design and architectures for dependable embedded systems. In Proceedings of the seventh IEEE/ACM/IFIP International Conference on Hardware/software Codesign and system synthesis - CODES+ISSS ’11.https://doi.org/10.1145/2039370.2039384 

Meyer, B., Plessl, C., &; Förstner, J. (2011). Transformation of scientific algorithms to parallel computing code: subdomain support in a MPI-multi-GPU backend. Symp. on Application Accelerators in High Performance Computing (SAAHPC), 60–63.https://doi.org/10.1109/SAAHPC.2011.12 

Beisel, T., Wiersema, T., Plessl, C., &; Brinkmann, A. (2011). Cooperative multitasking for heterogeneous accelerators in the Linux Completely Fair Scheduler. Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), 223–226.https://doi.org/10.1109/ASAP.2011.6043273 

Happe, M., Agne, A., &; Plessl, C. (2011). Measuring and Predicting Temperature Distributions on FPGAs at Run-Time. Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig), 55–60.https://doi.org/10.1109/ReConFig.2011.59 

Kenter, T., Platzner, M., Plessl, C., &; Kauschke, M. (2011). Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures. Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA), 177–180.https://doi.org/10.1145/1950413.1950448 

Schumacher, T., Süß, T., Plessl, C., &; Platzner, M. (2011). FPGA Acceleration of Communication-bound Streaming Applications: Architecture Modeling and a 3D Image Compositing Case Study. Int. Journal of Recon- Figurable Computing (IJRC).https://doi.org/10.1155/2011/760954 

Grad, M., &; Plessl, C. (2011). Just-in-time Instruction Set Extension – Feasibility and Limitations for an FPGA-based Reconfigurable ASIP Architecture. Proc. Reconfigurable Architectures Workshop (RAW), 278–285.https://doi.org/10.1109/IPDPS.2011.153 

Drzevitzky, S., Kastens, U., &; Platzner, M. (2010). Proof-Carrying Hardware: Concept and Prototype Tool Flow for Online Verification. International Journal of Reconfigurable Computing, 2010.https://doi.org/10.1155/2010/180242 

Agne, A. (2010). Virtuelle Speicherverwaltung für Hardware Threads in Rekonfigurierbaren Systemen. Paderborn University.

Boschmann, A. (2010). EMG-basierte Ganganalyse. Paderborn University.

Breitlauch, D. (2010). Evolvable Cache Controller. Paderborn University.

Dridger, D. (2010). Soft Microprocessors with tightly coupled Application-Specific Coprocessors. Paderborn University.

Graf, T. (2010). Parallelization of the UCT Algorithm on HPC-Clusters. Paderborn University.

Kaufmann, P., Englehart, K., &; Platzner, M. (2010). Fluctuating EMG Signals: Investigating Long-term Effects of Pattern Matching Algorithms. In International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC) (pp. 6357–6360). IEEE.

Kaufmann, P., Knieper, T., &; Platzner, M. (2010). A Novel Hybrid Evolutionary Strategy and its Periodization with Multi-objective Genetic Optimizers. In IEEE World Congress on Computational Intelligence (WCCI), Congress on Evolutionary Computation (CEC) (pp. 541–548). IEEE.

Kebschull, U., Platzner, M., &; Teich, J. (2010). Selected papers from the 18th International Conference on Field Programmable Logic and Applications, FPL 2008 (editorial). IET Computers Digital Techniques, 4(3), 157–158.https://doi.org/10.1049/iet-cdt.2010.9044