T. Kenter, C. Plessl, M. Platzner, and M. Kauschke, “Estimation and Partitioning for CPU-Accelerator Architectures,” in Intel European Research and Innovation Conference, 2011.
LibreCat: /record/2191

C. Plessl and M. Platzner, “Hardware Virtualization on Dynamically Reconfigurable Embedded Processors,” in Reconfigurable Embedded Control Systems: Applications for Flexibility and Agility, M. Khalgui and H.-M. Hanisch, Eds. Hershey, PA, USA: IGI Global, 2011.
LibreCat: /record/2202
DOI: 10.4018/978-1-60960-086-0

T. Graf, U. Lorenz, M. Platzner, and L. Schaefers, “Parallel Monte-Carlo Tree Search for HPC Systems,” in Proc. European Conf. on Parallel Processing (Euro-Par), 2011, vol. 6853.
LibreCat: /record/2204
DOI: 10.1007/978-3-642-23397-5_36

S. Drzevitzky and M. Platzner, “Achieving Hardware Security for Reconû01gurable Systems on Chip by a Proof-Carrying Code Approach,” in Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), 2011, pp. 58–65.
LibreCat: /record/666
DOI: 10.1109/ReCoSoC.2011.5981499

A. Boschmann, P. Kaufmann, and M. Platzner, “Accurate gait phase detection using surface electromyographic signals and support vector machines,” in Proc. IEEE Int. Conf. Bioinformatics and Biomedical Technology (ICBBT), 2011.
LibreCat: /record/10637

A. Boschmann, M. Platzner, M. Robrecht, M. Hahn, and M. Winkler, “Development of a pattern recognition-based myoelectric transhumeral prosthesis with multifunctional simultaneous control using a model-driven ppproach for mechatronic systems,” in Proc. MyoElectric Controls Symposium (MEC), 2011.
LibreCat: /record/10638

N. Ikonomakis, PinSim: Schnelle Simulation mit Pintools. Paderborn University, 2011.
LibreCat: /record/10678

H. Kassner, MPI-CUDA Codegenerierung für Nanophoton Simulationen auf Clustern. Paderborn University, 2011.
LibreCat: /record/10680

P. Kaufmann and M. Platzner, “Multi-objective Intrinsic Evolution of Embedded Systems,” in Organic Computing---A Paradigm Shift for Complex Systems, vol. 1, C. Müller-Schloer, H. Schmeck, and T. Ungerer, Eds. Springer Basel, 2011, pp. 193–206.
LibreCat: /record/10687

A. Schwabe, Analysis of Algorithmic Approaches for Temporal Partitioning. Paderborn University, 2011.
LibreCat: /record/10736

L. Sekanina, J. A. Walker, P. Kaufmann, C. Plessl, and M. Platzner, “Evolution of Electronic Circuits,” in Cartesian Genetic Programming, Springer Berlin Heidelberg, 2011, pp. 125–179.
LibreCat: /record/10737

J. A. Walker, J. F. Miller, P. Kaufmann, and M. Platzner, “Problem Decomposition in Cartesian Genetic Programming,” in Cartesian Genetic Programming, Springer Berlin Heidelberg, 2011, pp. 35–99.
LibreCat: /record/10748

D. Welp, User Space Scheduling for Heterogeneous Systems. Paderborn University, 2011.
LibreCat: /record/10750

A. Agne, M. Platzner, and E. Lübbers, “Memory Virtualization for Multithreaded Reconfigurable Hardware,” in Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), 2011, pp. 185–188.
LibreCat: /record/13643
DOI: 10.1109/fpl.2011.42

J. Henkel et al., “Design and architectures for dependable embedded systems,” in Proceedings of the seventh IEEE/ACM/IFIP International Conference on Hardware/software Codesign and system synthesis - CODES+ISSS ’11, 2011.
LibreCat: /record/13644
DOI: 10.1145/2039370.2039384

B. Meyer, C. Plessl, and J. Förstner, “Transformation of scientific algorithms to parallel computing code: subdomain support in a MPI-multi-GPU backend,”10.1109/SAAHPC.2011.12__in Symp. on Application Accelerators in High Performance Computing (SAAHPC), 2011, pp. 60–63, doi:10.1109/SAAHPC.2011.12 .
LibreCat: /record/2194
DOI: 10.1109/SAAHPC.2011.12

T. Beisel, T. Wiersema, C. Plessl, and A. Brinkmann, “Cooperative multitasking for heterogeneous accelerators in the Linux Completely Fair Scheduler,”10.1109/ASAP.2011.6043273__in Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), 2011, pp. 223–226, doi:10.1109/ASAP.2011.6043273 .
LibreCat: /record/2193
DOI: 10.1109/ASAP.2011.6043273

M. Happe, A. Agne, and C. Plessl, “Measuring and Predicting Temperature Distributions on FPGAs at Run-Time,”10.1109/ReConFig.2011.59__in Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig), 2011, pp. 55–60, doi:10.1109/ReConFig.2011.59 .
LibreCat: /record/656
DOI: 10.1109/ReConFig.2011.59

T. Kenter, M. Platzner, C. Plessl, and M. Kauschke, “Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures,”10.1145/1950413.1950448__in Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA), 2011, pp. 177–180, doi:10.1145/1950413.1950448 .
LibreCat: /record/2200
DOI: 10.1145/1950413.1950448

T. Schumacher, T. Süß, C. Plessl, and M. Platzner, “FPGA Acceleration of Communication-bound Streaming Applications: Architecture Modeling and a 3D Image Compositing Case Study,”10.1155/2011/760954__Int. Journal of Recon- figurable Computing (IJRC), 2011, doi:10.1155/2011/760954 .
LibreCat: /record/2201
DOI: 10.1155/2011/760954

M. Grad and C. Plessl, “Just-in-time Instruction Set Extension – Feasibility and Limitations for an FPGA-based Reconfigurable ASIP Architecture,”10.1109/IPDPS.2011.153__in Proc. Reconfigurable Architectures Workshop (RAW), 2011, pp. 278–285, doi:10.1109/IPDPS.2011.153 .
LibreCat: /record/2198
DOI: 10.1109/IPDPS.2011.153

S. Drzevitzky, U. Kastens, and M. Platzner, “Proof-Carrying Hardware: Concept and Prototype Tool Flow for Online Verification,” International Journal of Reconfigurable Computing, vol. 2010, 2010.
LibreCat: /record/10605
DOI: 10.1155/2010/180242

A. Agne, Virtuelle Speicherverwaltung für Hardware Threads in Rekonfigurierbaren Systemen. Paderborn University, 2010.
LibreCat: /record/10614

A. Boschmann, EMG-basierte Ganganalyse. Paderborn University, 2010.
LibreCat: /record/10629

D. Breitlauch, Evolvable Cache Controller. Paderborn University, 2010.
LibreCat: /record/10642

D. Dridger, Soft Microprocessors with tightly coupled Application-Specific Coprocessors. Paderborn University, 2010.
LibreCat: /record/10649

T. Graf, Parallelization of the UCT Algorithm on HPC-Clusters. Paderborn University, 2010.
LibreCat: /record/10657

P. Kaufmann, K. Englehart, and M. Platzner, “Fluctuating EMG Signals: Investigating Long-term Effects of Pattern Matching Algorithms,” in International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC), 2010, pp. 6357–6360.
LibreCat: /record/10683

P. Kaufmann, T. Knieper, and M. Platzner, “A Novel Hybrid Evolutionary Strategy and its Periodization with Multi-objective Genetic Optimizers,” in IEEE World Congress on Computational Intelligence (WCCI), Congress on Evolutionary Computation (CEC), 2010, pp. 541–548.
LibreCat: /record/10686

U. Kebschull, M. Platzner, and J. Teich, “Selected papers from the 18th International Conference on Field Programmable Logic and Applications, FPL 2008 (editorial),” IET Computers Digital Techniques, vol. 4, no. 3, pp. 157–158, 2010.
LibreCat: /record/10694
DOI: 10.1049/iet-cdt.2010.9044

T. Knieper, Hybridization of Global Multi-Objective and Local Search Techniques. Paderborn University, 2010.
LibreCat: /record/10697

T. Knieper, P. Kaufmann, K. Glette, M. Platzner, and J. Torresen, “Coping with Resource Fluctuations: The Run-time Reconfigurable Functional Unit Row Classifier Architecture,” in IEEE Intl. Conf. on Evolvable Systems (ICES), 2010, vol. 6274, pp. 250–261.
LibreCat: /record/10699

E. Lübbers and M. Platzner, “ReconOS: An Operating System for Dynamically Reconfigurable Hardware,” in Dynamically Reconfigurable Systems: Architectures, Design Methods and Applications, M. Platzner, J. Teich, and N. Wehn, Eds. Springer-Verlag GmbH, 2010, pp. 269–290.
LibreCat: /record/10704
DOI: 10.1007/978-90-481-3485-4_13

R. Meiche, FPGA/CPU Multicore-Plattform für ReconOS/eCos. Paderborn University, 2010.
LibreCat: /record/10710

M. Niekamp, Transparente Hardwarebeschleunigung durch Shared Library Interposing. Paderborn University, 2010.
LibreCat: /record/10717

B. Runde, A Token-Ring Network-On-Chip for Message Passing in ReconOS. Paderborn University, 2010.
LibreCat: /record/10731

T. Wiersema, Scheduling Support for Heterogeneous Hardware Accelerators under Linux. Paderborn University, 2010.
LibreCat: /record/10752

M. Platzner, J. Teich, and N. Wehn, Eds., Dynamically Reconfigurable Systems: Architectures, Design Methods and Applications. Springer-Verlag GmbH, 2010.
LibreCat: /record/10763
DOI: 10.1007/978-90-481-3485-4

M. Khatir, H. Ghasemzadeh Mohammadi, and A. Ejlali, “Sub-threshold charge recovery circuits,” in Computer Design (ICCD), 2010 IEEE International Conference on, 2010, pp. 138–144.
LibreCat: /record/10776
DOI: 10.1109/ICCD.2010.5647815

H. Giefers and M. Platzner, “A Triple Hybrid Interconnect for Many-Cores: Reconfigurable Mesh, NoC and Barrier,” in Proceedings of the 20th International Conference on Field Programmable Logic and Applications (FPL), 2010.
LibreCat: /record/13640

W. Schäfer et al., “Engineering Self-Coordinating Software Intensive Systems,” in Proceedings of the Foundations of Software Engineering (FSE) and NITR &; D/SPD Working Conference on the Future of Software Engineering Research (FoSER), 2010, pp. 321–324.
LibreCat: /record/13641

H. Giefers and M. Platzner, “A Self-Reconfigurable Lightweight Interconnect for Scalable Processor Fabrics,” in Proceedings of the 10th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2010.
LibreCat: /record/13642

E. Lübbers, M. Platzner, C. Plessl, A. Keller, and B. Plattner, “Towards Adaptive Networking for Embedded Devices based on Reconfigurable Hardware,” in Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2010, pp. 225–231.
LibreCat: /record/2223

M. Grad and C. Plessl, “Pruning the Design Space for Just-In-Time Processor Customization,”10.1109/ReConFig.2010.19__in Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), 2010, pp. 67–72, doi:10.1109/ReConFig.2010.19 .
LibreCat: /record/2216
DOI: 10.1109/ReConFig.2010.19

M. Grad and C. Plessl, “An Open Source Circuit Library with Benchmarking Facilities,” in Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2010, pp. 144–150.
LibreCat: /record/2224

D. Andrews and C. Plessl, “Configurable Processor Architectures: History and Trends,” in Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2010, p. 165.
LibreCat: /record/2220

T. P. Plaks et al., Eds., Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press, 2010.
LibreCat: /record/2222

T. Beisel, M. Niekamp, and C. Plessl, “Using Shared Library Interposing for Transparent Acceleration in Systems with Heterogeneous Hardware Accelerators,”10.1109/ASAP.2010.5540798__in Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), 2010, pp. 65–72, doi:10.1109/ASAP.2010.5540798 .
LibreCat: /record/2226
DOI: 10.1109/ASAP.2010.5540798

A. Keller, B. Plattner, E. Lübbers, M. Platzner, and C. Plessl, “Reconfigurable Nodes for Future Networks,”10.1109/GLOCOMW.2010.5700341__in Proc. IEEE Globecom Workshop on Network of the Future (FutureNet), 2010, pp. 372–376, doi:10.1109/GLOCOMW.2010.5700341 .
LibreCat: /record/2206
DOI: 10.1109/GLOCOMW.2010.5700341

T. Kenter, M. Platzner, C. Plessl, and M. Kauschke, “Performance Estimation for the Exploration of CPU-Accelerator Architectures,” in Proc. Workshop on Architectural Research Prototyping (WARP), International Symposium on Computer Architecture (ISCA), 2010.
LibreCat: /record/2228