Sekanina, L., Walker, J. A., Kaufmann, P., Plessl, C., &; Platzner, M. (2011). Evolution of Electronic Circuits. In Cartesian Genetic Programming (pp. 125–179). Springer Berlin Heidelberg.
LibreCat: /record/10737

Walker, J. A., Miller, J. F., Kaufmann, P., &; Platzner, M. (2011). Problem Decomposition in Cartesian Genetic Programming. In Cartesian Genetic Programming (pp. 35–99). Springer Berlin Heidelberg.
LibreCat: /record/10748

Welp, D. (2011). User Space Scheduling for Heterogeneous Systems. Paderborn University.
LibreCat: /record/10750

Agne, A., Platzner, M., &; Lübbers, E. (2011). Memory Virtualization for Multithreaded Reconfigurable Hardware. In Proceedings of the International Conference on Field Programmable Logic and Applications (FPL) (pp. 185–188). IEEE.https://doi.org/10.1109/fpl.2011.42 
LibreCat: /record/13643
DOI: 10.1109/fpl.2011.42

Henkel, J., Hedrich, L., Herkersdorf, A., Kapitza, R., Lohmann, D., Marwedel, P.,https://doi.org/10.1145/2039370.2039384__Härtig, H. (2011). Design and architectures for dependable embedded systems. In Proceedings of the seventh IEEE/ACM/IFIP International Conference on Hardware/software Codesign and system synthesis - CODES+ISSS ’11.https://doi.org/10.1145/2039370.2039384 
LibreCat: /record/13644
DOI: 10.1145/2039370.2039384

Meyer, B., Plessl, C., &; Förstner, J. (2011). Transformation of scientific algorithms to parallel computing code: subdomain support in a MPI-multi-GPU backend. Symp. on Application Accelerators in High Performance Computing (SAAHPC), 60–63.https://doi.org/10.1109/SAAHPC.2011.12 
LibreCat: /record/2194
DOI: 10.1109/SAAHPC.2011.12

Beisel, T., Wiersema, T., Plessl, C., &; Brinkmann, A. (2011). Cooperative multitasking for heterogeneous accelerators in the Linux Completely Fair Scheduler. Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), 223–226.https://doi.org/10.1109/ASAP.2011.6043273 
LibreCat: /record/2193
DOI: 10.1109/ASAP.2011.6043273

Happe, M., Agne, A., &; Plessl, C. (2011). Measuring and Predicting Temperature Distributions on FPGAs at Run-Time. Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig), 55–60.https://doi.org/10.1109/ReConFig.2011.59 
LibreCat: /record/656
DOI: 10.1109/ReConFig.2011.59

Kenter, T., Platzner, M., Plessl, C., &; Kauschke, M. (2011). Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures. Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA), 177–180.https://doi.org/10.1145/1950413.1950448 
LibreCat: /record/2200
DOI: 10.1145/1950413.1950448

Schumacher, T., Süß, T., Plessl, C., &; Platzner, M. (2011). FPGA Acceleration of Communication-bound Streaming Applications: Architecture Modeling and a 3D Image Compositing Case Study. Int. Journal of Recon- Figurable Computing (IJRC).https://doi.org/10.1155/2011/760954 
LibreCat: /record/2201
DOI: 10.1155/2011/760954

Grad, M., &; Plessl, C. (2011). Just-in-time Instruction Set Extension – Feasibility and Limitations for an FPGA-based Reconfigurable ASIP Architecture. Proc. Reconfigurable Architectures Workshop (RAW), 278–285.https://doi.org/10.1109/IPDPS.2011.153 
LibreCat: /record/2198
DOI: 10.1109/IPDPS.2011.153

Drzevitzky, S., Kastens, U., &; Platzner, M. (2010). Proof-Carrying Hardware: Concept and Prototype Tool Flow for Online Verification. International Journal of Reconfigurable Computing, 2010.https://doi.org/10.1155/2010/180242 
LibreCat: /record/10605
DOI: 10.1155/2010/180242

Agne, A. (2010). Virtuelle Speicherverwaltung für Hardware Threads in Rekonfigurierbaren Systemen. Paderborn University.
LibreCat: /record/10614

Boschmann, A. (2010). EMG-basierte Ganganalyse. Paderborn University.
LibreCat: /record/10629

Breitlauch, D. (2010). Evolvable Cache Controller. Paderborn University.
LibreCat: /record/10642

Dridger, D. (2010). Soft Microprocessors with tightly coupled Application-Specific Coprocessors. Paderborn University.
LibreCat: /record/10649

Graf, T. (2010). Parallelization of the UCT Algorithm on HPC-Clusters. Paderborn University.
LibreCat: /record/10657

Kaufmann, P., Englehart, K., &; Platzner, M. (2010). Fluctuating EMG Signals: Investigating Long-term Effects of Pattern Matching Algorithms. In International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC) (pp. 6357–6360). IEEE.
LibreCat: /record/10683

Kaufmann, P., Knieper, T., &; Platzner, M. (2010). A Novel Hybrid Evolutionary Strategy and its Periodization with Multi-objective Genetic Optimizers. In IEEE World Congress on Computational Intelligence (WCCI), Congress on Evolutionary Computation (CEC) (pp. 541–548). IEEE.
LibreCat: /record/10686

Kebschull, U., Platzner, M., &; Teich, J. (2010). Selected papers from the 18th International Conference on Field Programmable Logic and Applications, FPL 2008 (editorial). IET Computers Digital Techniques, 4(3), 157–158.https://doi.org/10.1049/iet-cdt.2010.9044 
LibreCat: /record/10694
DOI: 10.1049/iet-cdt.2010.9044

Knieper, T. (2010). Hybridization of Global Multi-Objective and Local Search Techniques. Paderborn University.
LibreCat: /record/10697

Knieper, T., Kaufmann, P., Glette, K., Platzner, M., &; Torresen, J. (2010). Coping with Resource Fluctuations: The Run-time Reconfigurable Functional Unit Row Classifier Architecture. In IEEE Intl. Conf. on Evolvable Systems (ICES) (Vol. 6274, pp. 250–261). Springer.
LibreCat: /record/10699

Lübbers, E., &; Platzner, M. (2010). ReconOS: An Operating System for Dynamically Reconfigurable Hardware. In M. Platzner, J. Teich, &; N. Wehn (Eds.), Dynamically Reconfigurable Systems: Architectures, Design Methods and Applications (pp. 269–290). Springer-Verlag GmbH.https://doi.org/10.1007/978-90-481-3485-4_13 
LibreCat: /record/10704
DOI: 10.1007/978-90-481-3485-4_13

Meiche, R. (2010). FPGA/CPU Multicore-Plattform für ReconOS/eCos. Paderborn University.
LibreCat: /record/10710

Niekamp, M. (2010). Transparente Hardwarebeschleunigung durch Shared Library Interposing. Paderborn University.
LibreCat: /record/10717

Runde, B. (2010). A Token-Ring Network-On-Chip for Message Passing in ReconOS. Paderborn University.
LibreCat: /record/10731

Wiersema, T. (2010). Scheduling Support for Heterogeneous Hardware Accelerators under Linux. Paderborn University.
LibreCat: /record/10752

Platzner, M., Teich, J., &; Wehn, N. (Eds.). (2010). Dynamically Reconfigurable Systems: Architectures, Design Methods and Applications. Springer-Verlag GmbH.https://doi.org/10.1007/978-90-481-3485-4 
LibreCat: /record/10763
DOI: 10.1007/978-90-481-3485-4

Khatir, M., Ghasemzadeh Mohammadi, H., &; Ejlali, A. (2010). Sub-threshold charge recovery circuits. In Computer Design (ICCD), 2010 IEEE International Conference on (pp. 138–144). IEEE.https://doi.org/10.1109/ICCD.2010.5647815 
LibreCat: /record/10776
DOI: 10.1109/ICCD.2010.5647815

Giefers, H., &; Platzner, M. (2010). A Triple Hybrid Interconnect for Many-Cores: Reconfigurable Mesh, NoC and Barrier. In Proceedings of the 20th International Conference on Field Programmable Logic and Applications (FPL). IEEE.
LibreCat: /record/13640

Schäfer, W., Birattari, M., Blömer, J., Dorigo, M., Engels, G., O’Grady, R.,  Trächtler, A. (2010). Engineering Self-Coordinating Software Intensive Systems. In Proceedings of the Foundations of Software Engineering (FSE) and NITR &; D/SPD Working Conference on the Future of Software Engineering Research (FoSER) (pp. 321–324).
LibreCat: /record/13641

Giefers, H., &; Platzner, M. (2010). A Self-Reconfigurable Lightweight Interconnect for Scalable Processor Fabrics. In Proceedings of the 10th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press.
LibreCat: /record/13642

Lübbers, E., Platzner, M., Plessl, C., Keller, A., &; Plattner, B. (2010). Towards Adaptive Networking for Embedded Devices based on Reconfigurable Hardware. Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 225–231.
LibreCat: /record/2223

Grad, M., &; Plessl, C. (2010). Pruning the Design Space for Just-In-Time Processor Customization. Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), 67–72.https://doi.org/10.1109/ReConFig.2010.19 
LibreCat: /record/2216
DOI: 10.1109/ReConFig.2010.19

Grad, M., &; Plessl, C. (2010). An Open Source Circuit Library with Benchmarking Facilities. Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 144–150.
LibreCat: /record/2224

Andrews, D., &; Plessl, C. (2010). Configurable Processor Architectures: History and Trends. Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 165.
LibreCat: /record/2220

Plaks, T. P., Andrews, D., DeMara, R., Lam, H., Lee, J., Plessl, C., &; Stitt, G. (Eds.). (2010). Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press.
LibreCat: /record/2222

Beisel, T., Niekamp, M., &; Plessl, C. (2010). Using Shared Library Interposing for Transparent Acceleration in Systems with Heterogeneous Hardware Accelerators. Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), 65–72.https://doi.org/10.1109/ASAP.2010.5540798 
LibreCat: /record/2226
DOI: 10.1109/ASAP.2010.5540798

Keller, A., Plattner, B., Lübbers, E., Platzner, M., &; Plessl, C. (2010). Reconfigurable Nodes for Future Networks. Proc. IEEE Globecom Workshop on Network of the Future (FutureNet), 372–376.https://doi.org/10.1109/GLOCOMW.2010.5700341 
LibreCat: /record/2206
DOI: 10.1109/GLOCOMW.2010.5700341

Kenter, T., Platzner, M., Plessl, C., &; Kauschke, M. (2010). Performance Estimation for the Exploration of CPU-Accelerator Architectures. In O. Hammami &; S. Larrabee (Eds.), Proc. Workshop on Architectural Research Prototyping (WARP), International Symposium on Computer Architecture (ISCA).
LibreCat: /record/2228

Boschmann, A., Kaufmann, P., Platzner, M., &; Winkler, M. (2009). Towards multi-movement hand prostheses: Combining adaptive classification with high precision sockets. In Proc. Technically Assisted Rehabilitation (TAR).
LibreCat: /record/10639

Kostin, A. (2009). Evolvable Robot Controller. Paderborn University.
LibreCat: /record/10702

Lübbers, E., &; Platzner, M. (2009). ReconOS: Multithreaded Programming for Reconfigurable Computers. ACM Transactions on Embedded Computing Systems, 9(1), 8:1-8:33.https://doi.org/10.1145/1596532.1596540 
LibreCat: /record/10703
DOI: 10.1145/1596532.1596540

Tofall, M. (2009). Compiler for a Custom Instruction Set CPU. Paderborn University.
LibreCat: /record/10746

Warkentin, A. (2009). Coarse-grained CGP Model using Xilinx Virte DSE Functional Units. Paderborn University.
LibreCat: /record/10749

Wildenhain, B. (2009). Implementierung von Kryptographie-Hardwarebeschleunigern für das HW/SW-Betriebssystem ReconOS. Paderborn University.
LibreCat: /record/10753

Ghasemzadeh Mohammadi, H., Miremadi, S. G., &; Ejlali, A. (2009). Signature Self Checking (SSC): A Low-Cost Reliable Control Logic for Pipelined Microprocessors. In Dependable Computing (PRDC), 2009 IEEE Pacific Rim International Symposium on (pp. 252–255). IEEE.https://doi.org/10.1109/PRDC.2009.69 
LibreCat: /record/10777
DOI: 10.1109/PRDC.2009.69

Happe, M., Lübbers, E., &; Platzner, M. (2009). A Multithreaded Framework for Sequential Monte Carlo Methods on CPU/FPGA Platforms. In Proceedings of the International Workshop on Applied Reconfigurable Computing (ARC). Springer.
LibreCat: /record/13632

Giefers, H., &; Platzner, M. (2009). Towards Models for Many-Cores: The Case for the Reconfigurable Mesh. In Proceedings of the Workshop on Many-Cores, International Conference on Architecture of Computing Systems (ARCS).
LibreCat: /record/13634

Giefers, H., &; Platzner, M. (2009). ARMLang: A Language and Compiler for Programming Reconfigurable Mesh Many-Cores. In Reconfigurable Architectures Workshop (RAW), Proceedings of the International Parallel and Distributed Processing Symposium. IEEE.
LibreCat: /record/13635