C. Kashikar, A Comparison of Machine Learning Techniques for the On-line Characterization of Tasks Executed on Heterogeneous Compute Nodes. Paderborn: Paderborn University, 2021.
LibreCat: /record/29151

M. Awais, H. Ghasemzadeh Mohammadi, and M. Platzner, “LDAX: A Learning-based Fast Design Space Exploration Framework for Approximate Circuit Synthesis,” in Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI) 2021, Virtual, 2021, pp. 27–32.
LibreCat: /record/21610
DOI: https://doi.org/10.1145/3453688.3461506

J. W. Rehnen, Decomposition of Arithmetic Components for the Approximate Circuit Synthesis with EvoApproxLib. 2021.
LibreCat: /record/22216

M. Awais and M. Platzner, “MCTS-Based Synthesis Towards Efficient Approximate Accelerators,” in Proceedings of IEEE Computer Society Annual Symposium on VLSI, Tampa, Florida USA (Virtual), 2021, pp. 384–389.
LibreCat: /record/22309

M. Brede, Implementation and Profiling of XCS in the Context of Embedded Systems. Paderborn: Paderborn University, 2021.
LibreCat: /record/22483

L. M. Witschen, T. Wiersema, M. Raeisi Nafchi, A. Bockhorn, and M. Platzner, “Timing Optimization for Virtual FPGA Configurations,”10.1007/978-3-030-79025-7_4__in Proceedings of International Symposium on Applied Reconfigurable Computing (ARC’21), Virtual conference, doi:10.1007/978-3-030-79025-7_4 .
LibreCat: /record/21953
DOI: 10.1007/978-3-030-79025-7_4

A. Boschmann, D. Neuhaus, S. Vogt, C. Kaltschmidt, M. Platzner, and S. Dosen, “Immersive augmented reality system for the training of pattern classification control with a myoelectric prosthesis,”10.1186/s12984-021-00822-6__Journal of NeuroEngineering and Rehabilitation, vol. 18, no. 1, Art. no. 25, 2021, doi:10.1186/s12984-021-00822-6 .
LibreCat: /record/30906
DOI: 10.1186/s12984-021-00822-6

A. Rodriguez, A. Otero, M. Platzner, and E. De la Torre, “Exploiting Hardware-Based Data-Parallel and Multithreading Models for Smart Edge Computing in Reconfigurable FPGAs,”10.1109/tc.2021.3107196__IEEE Transactions on Computers, pp. 1–1, 2021, doi:10.1109/tc.2021.3107196 .
LibreCat: /record/30907
DOI: 10.1109/tc.2021.3107196

T. Hansmeier, “Self-aware Operation of Heterogeneous Compute Nodes using the Learning Classifier System XCS,”10.1145/3468044.3468055__presented at the International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART ’21), Online, 2021, doi:10.1145/3468044.3468055 .
LibreCat: /record/29137
DOI: 10.1145/3468044.3468055

M. A. Sheikh, Design and Implementation of a ReconROS-based Obstacle Avoidance System. Paderborn University, 2021.
LibreCat: /record/29540

C. Lienen and M. Platzner, “Design of Distributed Reconfigurable Robotics Systems with ReconROS,” arXiv:2107.07208. 2021.
LibreCat: /record/22764

T. Hansmeier and M. Platzner, “An Experimental Comparison of Explore/Exploit Strategies for the Learning Classifier System XCS,”10.1145/3449726.3463159__in GECCO ’21: Proceedings of the Genetic and Evolutionary Computation Conference Companion, Lille, France, 2021, pp. 1639–1647, doi:10.1145/3449726.3463159 .
LibreCat: /record/21813
DOI: 10.1145/3449726.3463159

M.-C. Jakobs, F. Pauck, M. Platzner, H. Wehrheim, and T. Wiersema, “Software/Hardware Co-Verification for Custom Instruction Set Processors,”10.1109/ACCESS.2021.3131213__IEEE Access, 2021, doi:10.1109/ACCESS.2021.3131213 .
LibreCat: /record/27841
DOI: 10.1109/ACCESS.2021.3131213

Q. A. Ahmed, “Hardware Trojans in Reconfigurable Computing,”10.1109/vlsi-soc53125.2021.9606974__2021, doi:10.1109/vlsi-soc53125.2021.9606974 .
LibreCat: /record/29138
DOI: 10.1109/vlsi-soc53125.2021.9606974

Q. A. Ahmed, T. Wiersema, and M. Platzner, “Malicious Routing: Circumventing Bitstream-level Verification for FPGAs,”10.23919/DATE51398.2021.9474026__presented at the Design, Automation and Test in Europe Conference (DATE’21), Alpexpo | Grenoble, France, 2021, doi:10.23919/DATE51398.2021.9474026 .
LibreCat: /record/20681
DOI: 10.23919/DATE51398.2021.9474026

L. Clausing, “ReconO: High-Performance Embedded Computing for Industrial Analytics on a Reconfigurable System-on-Chip,”10.1145/3468044.3468056__2021, doi:10.1145/3468044.3468056 .
LibreCat: /record/30909
DOI: 10.1145/3468044.3468056

H. Ghasemzadeh Mohammadi et al., “FLight: FPGA Acceleration of Lightweight DNN Model Inference in Industrial Analytics,”https://doi.org/10.1007/978-3-030-93736-2_27__2021, doi:https://doi.org/10.1007/978-3-030-93736-2_27 .
LibreCat: /record/30908
DOI: https://doi.org/10.1007/978-3-030-93736-2_27

Z.  Guetttatfi, P. Kaufmann, and M. Platzner, “Optimal and Greedy Heuristic Approaches for Scheduling and Mapping of Hardware Tasks to Reconfigurable Computing Devices,” in Proceedings of the International Workshop on Applied Reconfigurable Computing (ARC), 2020.
LibreCat: /record/3583

K. Chandrakar, Comparison of Feature Selection Techniques to Improve Approximate Circuit Synthesis. 2020.
LibreCat: /record/21324

L.-S. Henke, Evaluation of a ReconOS-ROS Combination based on a Video Processing Application. 2020.
LibreCat: /record/21432

C. P. Gatica and M. Platzner, “Adaptable Realization of Industrial Analytics Functions on Edge-Devices using Reconfigurable Architectures,” in Machine Learning for Cyber Physical Systems (ML4CPS 2017), 2020.
LibreCat: /record/21584
DOI: 10.1007/978-3-662-59084-3_9

L. M. Witschen, T. Wiersema, and M. Platzner, “Proof-carrying Approximate Circuits,” IEEE Transactions On Very Large Scale Integration Systems, vol. 28, no. 9, pp. 2084–2088, 2020.
LibreCat: /record/17358
DOI: 10.1109/TVLSI.2020.3008061

N. Ho, P. Kaufmann, and M. Platzner, “Evolution of Application-Specific Cache Mappings,” International Journal of Hybrid intelligent Systems, 2020.
LibreCat: /record/17369

L. M. Witschen, T. Wiersema, and M. Platzner, “Search Space Characterization for AxC Synthesis,” Fifth Workshop on Approximate Computing (AxC 2020). .
LibreCat: /record/20748

C. Lienen, M. Platzner, and B. Rinner, “ReconROS: Flexible Hardware Acceleration for RO Applications,” in Proceedings of the 2020 International Conference on Field-Programmable Technology (FPT), 2020.
LibreCat: /record/20750

S. Thiele, Implementing Machine Learning Functions as PYNQ FPGA Overlays. 2020.
LibreCat: /record/20820

V. Jaganath, Extension and Evaluation of Python-based High-Level Synthesis Tool Flows. 2020.
LibreCat: /record/20821

T. Hansmeier, P. Kaufmann, and M. Platzner, “An Adaption Mechanism for the Error Threshold of XCSF,”10.1145/3377929.3398106__in GECCO ’20: Proceedings of the Genetic and Evolutionary Computation Conference Companion, Cancún, Mexico, 2020, pp. 1756–1764, doi:10.1145/3377929.3398106 .
LibreCat: /record/17063
DOI: 10.1145/3377929.3398106

J. Anwer, S. Meisner, and M. Platzner, “Dynamic Reliability Management for FPGA-Based Systems,” International Journal of Reconfigurable Computing, pp. 1–19, 2020.
LibreCat: /record/17092
DOI: 10.1155/2020/2808710

K. Bellman et al., “Self-aware Cyber-Physical Systems,” ACM Transactions on Cyber-Physical Systems, vol. Accepted for Publication, pp. 1–24, 2020.
LibreCat: /record/15836

M. Awais, H. Ghasemzadeh Mohammadi, and M. Platzner, “A Hybrid Synthesis Methodology for Approximate Circuits,” in Proceedings of the 30th ACM Great Lakes Symposium on VLSI (GLSVLSI) 2020, Beijing, China, 2020, pp. 421–426.
LibreCat: /record/16213
DOI: 10.1145/3386263.3406952

T. Hansmeier, P. Kaufmann, and M. Platzner, “Enabling XCSF to Cope with Dynamic Environments via an Adaptive Error Threshold,” in GECCO ’20: Proceedings of the Genetic and Evolutionary Computation Conference Companion, Cancún, Mexico, 2020, pp. 125–126.
LibreCat: /record/16363
DOI: 10.1145/3377929.3389968

A. Lösch and M. Platzner, “MigHEFT: DAG-based Scheduling of Migratable Tasks on Heterogeneous Compute Nodes,”10.1109/ipdpsw50202.2020.00012__2020, doi:10.1109/ipdpsw50202.2020.00012 .
LibreCat: /record/20838
DOI: 10.1109/ipdpsw50202.2020.00012

F. P. Jentzsch, Design and Implementation of a ReconOS-based TensorFlow Lite Delegate Architecture. 2020.
LibreCat: /record/21433

L. M. Witschen, T. Wiersema, H. Ghasemzadeh Mohammadi, M. Awais, and M. Platzner, “CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit Generation,” Microelectronics Reliability, vol. 99, pp. 277–290, 2019.
LibreCat: /record/3585
DOI: 10.1016/j.microrel.2019.04.003

L. M. Witschen, H. Ghasemzadeh Mohammadi, M. Artmann, and M. Platzner, “Jump Search: A Fast Technique for the Synthesis of Approximate Circuits,” Fourth Workshop on Approximate Computing (AxC 2019). .
LibreCat: /record/16853

L. M. Witschen, H. Ghasemzadeh Mohammadi, M. Artmann, and M. Platzner, “Jump Search: A Fast Technique for the Synthesis of Approximate Circuits,” in Proceedings of the 2019 on Great Lakes Symposium on VLSI  - GLSVLSI ’19, Tysons Corner, VA, USA, 2019.
LibreCat: /record/10577
DOI: 10.1145/3299874.3317998

A. Boschmann, A. Agne, G. Thombansen, L. M. Witschen, F. Kraus, and M. Platzner, “Zynq-based acceleration of robust high density myoelectric signal processing,” Journal of Parallel and Distributed Computing, vol. 123, pp. 77–89, 2019.
LibreCat: /record/11950
DOI: 10.1016/j.jpdc.2018.07.004

T. Hansmeier, M. Platzner, M. J. H. Pantho, and D. Andrews, “An Accelerator for Resolution Proof Checking based on FPGA and Hybrid Memory Cube Technology,” Journal of Signal Processing Systems, vol. 91, no. 11, pp. 1259–1272, 2019.
LibreCat: /record/12967
DOI: 10.1007/s11265-018-1435-y

N. Ho, P. Kaufmann, and M. Platzner, “Optimization of Application-specific L1 Cache Translation Functions of the LEON3 Processor,” in World Congress on Nature and Biologically Inspired Computing (NaBIC), 2019.
LibreCat: /record/15422

S. Kumar Jeyakumar, Incremental learning with Support Vector Machine on embedded platforms. 2019.
LibreCat: /record/15883

M. Keerthipati, A Bitstream-Level Proof-Carrying Hardware Technique for Information Flow Tracking. Universität Paderborn, 2019.
LibreCat: /record/15920

N. S. Sabu, FPGA Acceleration of String Search Techniques in Huge Data Sets. Paderborn University, 2019.
LibreCat: /record/14831

J. Mehta, Multithreaded Software/Hardware Programming with ReconOS/freeRTOS on a Reconfc03gurable System-on-Chip. 2019.
LibreCat: /record/15946

T. Hansmeier, Autonomous Operation of High-Performance Compute Nodes through Self-Awareness and Learning Classifiers. Universität Paderborn, 2019.
LibreCat: /record/14546

Z. Guettatfi, M. Platzner, O. Kermia, and A. Khouas, “An Approach for Mapping Periodic Real-Time Tasks to Reconfigurable Hardware,”10.1109/ipdpsw.2019.00027__2019, doi:10.1109/ipdpsw.2019.00027 .
LibreCat: /record/31067
DOI: 10.1109/ipdpsw.2019.00027

Q. A. Ahmed, T. Wiersema, and M. Platzner, “Proof-Carrying Hardware Versus the Stealthy Malicious LUT Hardware Trojan,”10.1007/978-3-030-17227-5_10__in Applied Reconfigurable Computing, Darmstadt, Germany, 2019, vol. 11444, pp. 127–136, doi:10.1007/978-3-030-17227-5_10 .
LibreCat: /record/9913
DOI: 10.1007/978-3-030-17227-5_10

C. Lienen, Implementing a Real-time System on a Platform FPGA operated with ReconOS. Universität Paderborn.
LibreCat: /record/15874

M. Platzner and C. Plessl, “FPGAs im Rechenzentrum,”10.1007/s00287-019-01187-w__Informatik Spektrum, 2019, doi:10.1007/s00287-019-01187-w .
LibreCat: /record/12871
DOI: 10.1007/s00287-019-01187-w

J. D. Mehta, Multithreaded Software/Hardware Programming with ReconOS/freeRTOS on a Reconfigurable System-on-Chip. 2019.
LibreCat: /record/52478