Engineering Self-Coordinating Software Intensive Systems
W. Schäfer, M. Birattari, J. Blömer, M. Dorigo, G. Engels, R. O’Grady, M. Platzner, F.-J. Rammig, W. Reif, A. Trächtler, in: Proceedings of the Foundations of Software Engineering (FSE) and NITR &; D/SPD Working Conference on the Future of Software Engineering Research (FoSER), 2010, pp. 321–324.
LibreCat: /record/13641

A Self-Reconfigurable Lightweight Interconnect for Scalable Processor Fabrics
H. Giefers, M. Platzner, in: Proceedings of the 10th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2010.
LibreCat: /record/13642

Towards Adaptive Networking for Embedded Devices based on Reconfigurable Hardware
E. Lübbers, M. Platzner, C. Plessl, A. Keller, B. Plattner, in: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2010, pp. 225–231.
LibreCat: /record/2223

Pruning the Design Space for Just-In-Time Processor Customization
M. Grad, C. Plessl, in: Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), IEEE Computer Society, Los Alamitos, CA, USA, 2010, pp. 67–72.
LibreCat: /record/2216
DOI: 10.1109/ReConFig.2010.19

An Open Source Circuit Library with Benchmarking Facilities
M. Grad, C. Plessl, in: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2010, pp. 144–150.
LibreCat: /record/2224

Configurable Processor Architectures: History and Trends
D. Andrews, C. Plessl, in: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2010, p. 165.
LibreCat: /record/2220

Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)
T.P. Plaks, D. Andrews, R. DeMara, H. Lam, J. Lee, C. Plessl, G. Stitt, eds., Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2010.
LibreCat: /record/2222

Using Shared Library Interposing for Transparent Acceleration in Systems with Heterogeneous Hardware Accelerators
T. Beisel, M. Niekamp, C. Plessl, in: Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), IEEE Computer Society, 2010, pp. 65–72.
LibreCat: /record/2226
DOI: 10.1109/ASAP.2010.5540798

Reconfigurable Nodes for Future Networks
A. Keller, B. Plattner, E. Lübbers, M. Platzner, C. Plessl, in: Proc. IEEE Globecom Workshop on Network of the Future (FutureNet), IEEE, 2010, pp. 372–376.
LibreCat: /record/2206
DOI: 10.1109/GLOCOMW.2010.5700341

Performance Estimation for the Exploration of CPU-Accelerator Architectures
T. Kenter, M. Platzner, C. Plessl, M. Kauschke, in: O. Hammami, S. Larrabee (Eds.), Proc. Workshop on Architectural Research Prototyping (WARP), International Symposium on Computer Architecture (ISCA), 2010.
LibreCat: /record/2228

Towards multi-movement hand prostheses: Combining adaptive classification with high precision sockets
A. Boschmann, P. Kaufmann, M. Platzner, M. Winkler, in: Proc. Technically Assisted Rehabilitation (TAR), 2009.
LibreCat: /record/10639

Evolvable Robot Controller
A. Kostin, Evolvable Robot Controller, Paderborn University, 2009.
LibreCat: /record/10702

ReconOS: Multithreaded Programming for Reconfigurable Computers
E. Lübbers, M. Platzner, ACM Transactions on Embedded Computing Systems 9 (2009) 8:1-8:33.
LibreCat: /record/10703
DOI: 10.1145/1596532.1596540

Compiler for a Custom Instruction Set CPU
M. Tofall, Compiler for a Custom Instruction Set CPU, Paderborn University, 2009.
LibreCat: /record/10746

Coarse-grained CGP Model using Xilinx Virte DSE Functional Units
A. Warkentin, Coarse-Grained CGP Model Using Xilinx Virte DSE Functional Units, Paderborn University, 2009.
LibreCat: /record/10749

Implementierung von Kryptographie-Hardwarebeschleunigern für das HW/SW-Betriebssystem ReconOS
B. Wildenhain, Implementierung von Kryptographie-Hardwarebeschleunigern Für Das HW/SW-Betriebssystem ReconOS, Paderborn University, 2009.
LibreCat: /record/10753

Signature Self Checking (SSC): A Low-Cost Reliable Control Logic for Pipelined Microprocessors
H. Ghasemzadeh Mohammadi, S.G. Miremadi, A. Ejlali, in: Dependable Computing (PRDC), 2009 IEEE Pacific Rim International Symposium On, IEEE, 2009, pp. 252–255.
LibreCat: /record/10777
DOI: 10.1109/PRDC.2009.69

A Multithreaded Framework for Sequential Monte Carlo Methods on CPU/FPGA Platforms
M. Happe, E. Lübbers, M. Platzner, in: Proceedings of the International Workshop on Applied Reconfigurable Computing (ARC), Springer, 2009.
LibreCat: /record/13632

Towards Models for Many-Cores: The Case for the Reconfigurable Mesh
H. Giefers, M. Platzner, in: Proceedings of the Workshop on Many-Cores, International Conference on Architecture of Computing Systems (ARCS), 2009.
LibreCat: /record/13634

ARMLang: A Language and Compiler for Programming Reconfigurable Mesh Many-Cores
H. Giefers, M. Platzner, in: Reconfigurable Architectures Workshop (RAW), Proceedings of the International Parallel and Distributed Processing Symposium, IEEE, 2009.
LibreCat: /record/13635

Cooperative Multithreading in Dynamically Reconfigurable Systems
E. Lübbers, M. Platzner, in: Proceedings of the 19th International Workshop on Field Programmable Logic and Applications (FPL) , IEEE, 2009.
LibreCat: /record/13636

Program-driven Fine-grained Power Management for the Reconfigurable Mesh
H. Giefers, M. Platzner, in: Proceedings of the 19th International Workshop on Field Programmable Logic and Applications (FPL) , IEEE, 2009.
LibreCat: /record/13637

An adaptive Sequential Monte Carlo framework with runtime HW/SW repartitioning
M. Happe, E. Lübbers, M. Platzner, in: Proceedings of the 2009 International Conference on Field-Programmable Technology (FPT), IEEE, 2009.
LibreCat: /record/13638
DOI: 10.1109/fpt.2009.5377645

Proof-carrying Hardware: Towards Runtime Verification of Reconfigurable Modules
S. Drzevitzky, U. Kastens, M. Platzner, in: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2009.
LibreCat: /record/13639

IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing
T. Schumacher, C. Plessl, M. Platzner, in: Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), IEEE Computer Society, 2009, pp. 275–278.
LibreCat: /record/2350
DOI: 10.1109/FCCM.2009.25

EvoCaches: Application-specific Adaptation of Cache Mapping
P. Kaufmann, C. Plessl, M. Platzner, in: Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS), IEEE Computer Society, Los Alamitos, CA, USA, 2009, pp. 11–18.
LibreCat: /record/2262

Communication Performance Characterization for Reconfigurable Accelerator Design on the 
T. Schumacher, T. Süß, C. Plessl, M. Platzner, in: Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), IEEE Computer Society, Los Alamitos, CA, USA, 2009, pp. 119–124.
LibreCat: /record/2238
DOI: 10.1109/ReConFig.2009.32

An Accelerator for k-th Nearest Neighbor Thinning Based on the IMORC Infrastructure
T. Schumacher, C. Plessl, M. Platzner, in: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), IEEE, 2009, pp. 338–344.
LibreCat: /record/2261

Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX
M. Grad, C. Plessl, in: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, USA, 2009, pp. 319–322.
LibreCat: /record/2263

A method for OSEM PET reconstruction on parallel architectures using STIR
T. Beisel, S. Lietsch, K. Thielemans, in: IEEE Nuclear Science Symposium Conference Record (NSS), IEEE, 2008, pp. 4161–4168.
LibreCat: /record/2358
DOI: 10.1109/NSSMIC.2008.4774198

The GOmputer: Accelerating GO with FPGAs
M. Platzner, S. Döhre, M. Happe, T. Kenter, U. Lorenz, T. Schumacher, A. Send, A. Warkentin, in: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2008, pp. 245–251.
LibreCat: /record/2365

Aufbau und experimentelle Bewertung eines Systems zur Langzeitklassiû01kation von EMG-Signalen
A. Boschmann, Aufbau Und Experimentelle Bewertung Eines Systems Zur Langzeitklassiû01kation von EMG-Signalen, Paderborn University, 2008.
LibreCat: /record/10628

Selbstoptimierender Cache-Kontroller
D. Breitlauch, Selbstoptimierender Cache-Kontroller, Paderborn University, 2008.
LibreCat: /record/10641

Verteilte Simulation von mobilen Robotern mit EyeSim
T. Ceylan, C. Yalcin, Verteilte Simulation von Mobilen Robotern Mit EyeSim, Paderborn University, 2008.
LibreCat: /record/10644

Comparing Evolvable Hardware to Conventional Classifiers for Electromyographic Prosthetic Hand Control
K. Glette, T. Gruber, P. Kaufmann, J. Torresen, B. Sick, M. Platzner, in: IEEE Adaptive Hardware and Systems (AHS), IEEE, 2008, pp. 32–39.
LibreCat: /record/10653

A Comparison of Evolvable Hardware Architectures for Classification Tasks
K. Glette, J. Torresen, P. Kaufmann, M. Platzner, in: IEEE Intl. Conf. on Evolvable Systems (ICES), Springer, 2008, pp. 22–33.
LibreCat: /record/10656

Parallelisierung und Hardware- / Software - Codesign von Partikelfiltern
M. Happe, Parallelisierung Und Hardware- / Software - Codesign von Partikelfiltern, Paderborn University, 2008.
LibreCat: /record/10669

Evolvable Hardware - Tutorial at Architecture of Computing Systems (ARCS)
J. Torresen, K. Glette, M. Platzner, P. Kaufmann, (2008).
LibreCat: /record/10690

Advanced Techniques for the Creation and Propagation of Modules in Cartesian Genetic Programming
P. Kaufmann, M. Platzner, in: Genetic and Evolutionary Computation (GECCO), ACM Press, 2008, pp. 1219–1226.
LibreCat: /record/10691

Implementierung und Bewertung des multikriteriellen Optimierungsverfahrens IBEA für den automatisierten Schaltungsentwurf
T. Knieper, Implementierung Und Bewertung Des Multikriteriellen Optimierungsverfahrens IBEA Für Den Automatisierten Schaltungsentwurf, Paderborn University, 2008.
LibreCat: /record/10696

On Robust Evolution of Digital Hardware
T. Knieper, B. Defo, P. Kaufmann, M. Platzner, in: Biologically Inspired Collaborative Computing (BICC), Springer, 2008, pp. 2313–222.
LibreCat: /record/10698

Eine Monitoring- und Debugging-Infrastruktur für hybride HW/SW-Systeme
J. Niklas, Eine Monitoring- Und Debugging-Infrastruktur Für Hybride HW/SW-Systeme, Paderborn University, 2008.
LibreCat: /record/10718

Raytracing on a Custom Instruction Set CPU
M. Östermann, Raytracing on a Custom Instruction Set CPU, Paderborn University, 2008.
LibreCat: /record/10721

Design and Evaluation of MicroBlaze Multi-core Architectures
N. Westerheide, Design and Evaluation of MicroBlaze Multi-Core Architectures, Paderborn University, 2008.
LibreCat: /record/10751

A cost-effective error detection and roll-back recovery technique for embedded microprocessor control logic
H. Ghasemzadeh Mohammadi, H. Tabkhi, S.G. Miremadi, A. Ejlali, in: 2008 International Conference on Microelectronics, IEEE, 2008, pp. 444–447.
LibreCat: /record/10778
DOI: 10.1109/ICM.2008.5393497

Realizing Reconfigurable Mesh Algorithms on Softcore Arrays
H. Giefers, M. Platzner, in: Proceedings of the International Symposium on Systems, Architectures, Modeling and Simulation (SAMOS), IEEE, 2008.
LibreCat: /record/13629

Communication and Synchronization in Multithreaded Reconfigurable Computing Systems
E. Lübbers, M. Platzner, in: Proceedings of the 8th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2008.
LibreCat: /record/13630

A portable abstraction layer for hardware threads
E. Lübbers, M. Platzner, in: Proceedings of the 18th International Conference on Field Programmable Logic and Applications (FPL), IEEE, 2008.
LibreCat: /record/13631
DOI: 10.1109/fpl.2008.4629901

A Hardware Accelerator for k-th Nearest Neighbor Thinning
T. Schumacher, R. Meiche, P. Kaufmann, E. Lübbers, C. Plessl, M. Platzner, in: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2008, pp. 245–251.
LibreCat: /record/2364

IMORC: An infrastructure for performance monitoring and optimization of reconfigurable computers
T. Schumacher, C. Plessl, M. Platzner, in: Many-Core and Reconfigurable Supercomputing Conference (MRSC), 2008.
LibreCat: /record/2372