Walder H, Platzner M. Online scheduling for block-partitioned reconfigurable devices. In: Proceedings Design, Automation and Test in Europe Conference (DATE). IEEE CS Press; 2003:290-295. doi:10.1109/date.2003.1253622
LibreCat: /record/13612
DOI: 10.1109/date.2003.1253622

Walder H, Steiger C, Platzner M. Fast online task placement on FPGAs: free space partitioning and 2D-hashing. In: Proceedings International Parallel and Distributed Processing Symposium. IEEE CS Press; 2003. doi:10.1109/ipdps.2003.1213329
LibreCat: /record/13613
DOI: 10.1109/ipdps.2003.1213329

Walder H, Platzner M. Reconfigurable Hardware Operating Systems: From Design Concepts to Realizations. In: Proceedings of the 3rd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press; 2003:284-287.
LibreCat: /record/13614

Steiger C, Walder H, Platzner M. Heuristics for Online Scheduling Real-Time Tasks to Partially Reconfigurable Devices. In: Proceedings of the 13th International Conference on Field Programmable Logic and Applications (FPL). Berlin, Heidelberg: Springer; 2003:575-584. doi:10.1007/978-3-540-45234-8_56
LibreCat: /record/13615
DOI: 10.1007/978-3-540-45234-8_56

Steiger C, Walder H, Platzner M, Thiele L. Online scheduling and placement of real-time tasks to partially reconfigurable devices. In: Proceedings 24th IEEE International Real-Time Systems Symposium (RTSS). IEEE CS Press; 2003:252-235. doi:10.1109/real.2003.1253269
LibreCat: /record/13617
DOI: 10.1109/real.2003.1253269

Plessl C, Enzler R, Walder H, Beutel J, Platzner M, Thiele L. Reconfigurable Hardware in Wearable Computing Nodes. In: Proc. Int. Symp. on Wearable Computers (ISWC). IEEE Computer Society; 2002:215-222. doi:10.1109/ISWC.2002.1167250
LibreCat: /record/2423
DOI: 10.1109/ISWC.2002.1167250

Dyer M, Plessl C, Platzner M. Partially Reconfigurable Cores for Xilinx Virtex. In: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL). Vol 2438. Lecture Notes in Computer Science (LNCS). Springer; 2002:292-301. doi:10.1007/3-540-46117-5
LibreCat: /record/2424
DOI: 10.1007/3-540-46117-5

Plessl C, Platzner M. Custom Computing Machines for the Set Covering Problem. In: Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM). IEEE Computer Society; 2002:163-172. doi:10.1109/FPGA.2002.1106671
LibreCat: /record/2425
DOI: 10.1109/FPGA.2002.1106671

Eisenring M, Platzner M. A Framework for Run-time Reconfigurable Systems. The Journal of Supercomputing. 2002;21(2):145-159. doi:10.1023/a:1013627403946
LibreCat: /record/10651
DOI: 10.1023/a:1013627403946

Walder H, Platzner M. Non-preemptive Multitasking on FPGAs: Task Placement and Footprint Transform. In: Proceedings of the 2nd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press; 2002:24-30.
LibreCat: /record/13611

Plessl C, Platzner M. Instance-Specific Accelerators for Minimum Covering. In: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press; 2001:85-91.
LibreCat: /record/2428

Enzler R, Platzner M, Plessl C, Thiele L, Tröster G. Reconfigurable Processors for Handhelds and Wearables: Application Analysis. In: Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III. Vol 4525. Proc. SPIE. ; 2001:135-146. doi:10.1117/12.434376
LibreCat: /record/2432
DOI: 10.1117/12.434376

Mencer O, Platzner M, Morf M, J. Flynn M. Object-oriented domain specific compilers for programming FPGAs. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2001;9(1):205-210. doi:10.1109/92.920835
LibreCat: /record/10713
DOI: 10.1109/92.920835

Enzler R, Platzner M. Dynamically Reconfigurable Processors. TELEMATIK, Zeitschrift des Telematik-Ingebieur-Verbandes 7(1); 2001.
LibreCat: /record/13463

Platzner M. Reconfigurable accelerators for combinatorial problems. Computer. 2000;33(4):58-60. doi:10.1109/2.839322
LibreCat: /record/6507
DOI: 10.1109/2.839322

Eisenring M, Platzner M. Synthesis of Interfaces and Communication in Reconfigurable Embedded Systems. IEE Proceedings -- Computers &; Digital Techniques. 2000;147:159-165. doi:10.1049/ip-cdt:20000496
LibreCat: /record/10606
DOI: 10.1049/ip-cdt:20000496

Platzner M, Rinner B, Weiss R. Toward embedded qualitative simulation: a specialized computer architecture for QSim. IEEE Intelligent Systems. 2000;15(2):62-68. doi:10.1109/5254.850829
LibreCat: /record/10725
DOI: 10.1109/5254.850829

Eisenring MH, Platzner M. An Implementation Framework for Run-time Reconfigurable Systems. In: Proceedings of the 2nd International Workshop on Engineering of Reconfigurable Hardware/Software Objects (ENREGLE). CSREA Press; 2000:151-157.
LibreCat: /record/13609

Eisenring M, Platzner M. Optimization of Run-time Reconfigurable Embedded Systems. In: Proceedings of the 10th International Workshop on Field Programmable Logic and Applications (FPL). Springer; 2000:565-574.
LibreCat: /record/13610

Mencer O, Platzner M. Dynamic circuit generation for Boolean satisfiability in an object-oriented design environment. In: Proceedings of the 32nd Annual Hawaii International Conference on Systems Sciences (HICSS-32). IEEE CS Press; 1999. doi:10.1109/hicss.1999.772883
LibreCat: /record/13607
DOI: 10.1109/hicss.1999.772883

Eisenring M, Platzner M, Thiele L. Communication Synthesis for Reconfigurable Embedded Systems. In: Proceedings of the 9th International Workshop on Field Programmable Logic and Applications (FPL). Vol 1673. LCS. Springer; 1999:205-214. doi:10.1007/978-3-540-48302-1_21
LibreCat: /record/13608
DOI: 10.1007/978-3-540-48302-1_21

Platzner M. Reconfigurable Computer Architectures. e&;i Elektrotechnik und Informationstechnik. 1998;115:143-148.
LibreCat: /record/10607

Platzner M, Rinner B. Design and Implementation of a Parallel Constraint Satisfaction Algorithm. International Journal of Computers &; Their Applications. 1998;5:106-116.
LibreCat: /record/10608

Platzner M, Rinner B, Weiss R. A Distributed Computer Architecture for Fast Qualitative Simulation . Texas Instruments, The Elite Yearbook 1997 - Digital Signal Processing Solutions from Europe’s leading Universities; 1998:106-107.
LibreCat: /record/13464

Platzner M, De Micheli G. Acceleration of satisfiability algorithms by reconfigurable hardware. In: Proceedings of the 8th International Workshop on Field Programmable Logic and Applications (FPL) . LNCS. Berlin, Heidelberg: Springer ; 1998:69-78. doi:10.1007/bfb0055234
LibreCat: /record/13606
DOI: 10.1007/bfb0055234

Platzner M, Rinner B, Weiss R. A Computer Architecture to Support Qualitative Simulation in Industrial Applications. e &; i Elektrotechnik und Informationstechnik. 1997;114:13-18.
LibreCat: /record/10609

Platzner M, Rinner B, Weiss R. Parallel qualitative simulation. Simulation Practice and Theory. 1997;5(7-8):623-638. doi:10.1016/s0928-4869(97)00008-6
LibreCat: /record/10724
DOI: 10.1016/s0928-4869(97)00008-6

Platzner M, Peters L. Fast Signature Segmentation on a Multi-DSP Architecture. In: Proceedings of the SPIE: Conference on Parallel and Distributed Methods for Image Processing. Vol 3166. ; 1997.
LibreCat: /record/13603

Röwekamp T, Platzner M, Peters L. Specialized Architectures for Optical Flow Computation: A Performance Comparison of ASIC, DSP, and Multi-DSP. In: Proceedings of the 8th International Conference on Signal Processing Applications &; Technology (ICSPAT). ; 1997:829-833.
LibreCat: /record/13604

Lind E, Platzner M, Rinner B. A Multi-DSP System with Dynamically Reconfigurable Processors. In: Proceedings of the 7th International Conference on Signal Processing Applications &; Technology (ICSPAT). ; 1996.
LibreCat: /record/13602

Platzner M, Rinner B, Weiss R. Exploiting Parallelism in Constraint Satisfaction for Qualitative Simulation. JUCS Journal of Universal Computer Science. 1995;12:811-820.
LibreCat: /record/10610

Platzner M, Rinner B, Weiss R. A Distributed Computer Architecture for Qualitative Simulation based on a Multi-DSP and FPGAs. In: Proceedings of the 3rd Euromicro Workshop on Parallel and Distributed Processing . IEEE CS Press; 1995:311-318.
LibreCat: /record/13469

Brenner E, Ginthör-Kalcsics R, Hranitzky R, et al. High-Performance Simulators Based on Multi-TM0. In: Proceedings of the 5th Annual Texas Instruments TM0 Educators Conference. ; 1995.
LibreCat: /record/13470

Friedl G, Platzner M, Rinner B. A Special-Purpose Coprocessor for Qualitative Simulation. In: Proceedings of the EURO-PAR’95 International Conference on Parallel Processing. Springer International Publishing; 1995:695-698.
LibreCat: /record/13471

Platzner M, Rinner B, Weiss R. Parallel Qualitative Simulation. In: Proceedings of the EUROSIM Congress. Elsevier; 1995:231-236.
LibreCat: /record/13472

Platzner M, Rinner B. Improving Performance of the Qualitative Simulator QSIM - Design and Implementation of a Specialized Computer Architecture. In: Proceedings of the PDCS International Conference on Parallel and Distributed Computing Systems. ISCA; 1995:494-501.
LibreCat: /record/13473

Platzner M, Rinner B. High-Performance Qualitative Simulation on a Multi-DSP Architecture. In: Proceedings of the 6th International Conference on Signal Processing Applications &; Technology (ICSPAT). ; 1995.
LibreCat: /record/13474

Hranitzky R, Platzner M. Design and Implementation of Adaptive Digital Filters on a Multi-TM0 System. In: Proceedings of the 6th International Conference on Signal Processing Applications &; Technology (ICSPAT). ; 1995.
LibreCat: /record/13484

Platzner M, Steger C, Weiss R. Experimental Evaluation of Multi-DSP Architectures in High Performance Applications. In: Proceedings of the 7th Mediterranean Electrotechnical Conference. IEEE Press; 1994.
LibreCat: /record/13468

Platzner M, Steger C. Erfahrungen mit einer Multi-Signalprozessorarchitektur (TM0). Mikroelektronik. 1993.
LibreCat: /record/13466

Platzner M, Steger C, Weiss R. Performance Measurements on a Multi-DSP Architecture with TM0. In: Proceedings of the 4th International Conference on Signal Processing Applications &; Technology (ICSPAT). DSP Associates; 1993.
LibreCat: /record/13467

Ginthör R, Platzner M, Weiss R. Experimental Results to Interprocessor Communication in Distributed Transputer-Systems. In: Proceedings of the 1st Austrian-Hungarian Workshop on Transputer Applications. ; 1992:45-54.
LibreCat: /record/13465