Memory Security in Reconfigurable Computers: Combining Formal Verification with Monitoring
T. Wiersema, S. Drzevitzky, M. Platzner, in: Proceedings of the International Conference on Field-Programmable Technology (FPT), 2014, pp. 167–174.

Integrating Software and Hardware Verification
M.-C. Jakobs, M. Platzner, T. Wiersema, H. Wehrheim, in: E. Albert, E. Sekerinski (Eds.), Proceedings of the 11th International Conference on Integrated Formal Methods (IFM), 2014, pp. 307–322.

Embedding FPGA Overlays into Configurable Systems-on-Chip: ReconOS meets ZUMA
T. Wiersema, A. Bockhorn, M. Platzner, in: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 2014, pp. 1–6.

A Novel Technique and its Application to Computer Go
L. Schaefers, M. Platzner, IEEE Transactions on Computational Intelligence and AI in Games 6 (2014) 361–374.

An FPGA-based Reconfigurable Mesh Many-Core
H. Giefers, M. Platzner, IEEE Transactions on Computers 63 (2014) 2919–2932.

FPGA Redundancy Configurations: An Automated Design Space Exploration
J. Anwer, M. Platzner, S. Meisner, in: Reconfigurable Architectures Workshop (RAW), 2014.

Echtzeit Klassifikation von sEMG Signalen mit einem low-cost DSP Evaluation Board
A. Bockhorn, Echtzeit Klassifikation von SEMG Signalen Mit Einem Low-Cost DSP Evaluation Board, Paderborn University, 2014.

A computer vision-based approach to high density EMG pattern recognition using structural similarity
A. Boschmann, M. Platzner, in: Proc. MyoElectric Controls Symposium (MEC), 2014.

Towards robust HD EMG pattern recognition: Reducing electrode displacement effect using structural similarity
A. Boschmann, M. Platzner, in: Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC), 2014.

A Generalized Loop Accelerator Implemented as a Coarse-Grained Array
M. Brand, A Generalized Loop Accelerator Implemented as a Coarse-Grained Array, Paderborn University, 2014.

Easy-to-use-on-the-fly binary program acceleration on many-cores
M. Damschen, Easy-to-Use-on-the-Fly Binary Program Acceleration on Many-Cores, Paderborn University, 2014.

Lookup Table Partial Reconfiguration for an Evolvable Hardware Classifier System
K. Glette, P. Kaufmann, in: IEEE Congress on Evolutionary Computation (CEC), 2014.

Entwicklung einer codegrößenoptimierten Softwarebibliothek für 8-Bit Mikrocontroller in netzunabhängigen Notleuchten
C. Hagedorn, Entwicklung Einer Codegrößenoptimierten Softwarebibliothek Für 8-Bit Mikrocontroller in Netzunabhängigen Notleuchten, Paderborn University, 2014.

A hardware/software infrastructure for performance monitoring on LEON3 multicore platforms
N. Ho, P. Kaufmann, M. Platzner, in: 24th Intl. Conf. on Field Programmable Logic and Applications (FPL), 2014, pp. 1–4.

Towards self-adaptive caches: A run-time reconfigurable multi-core infrastructure
N. Ho, P. Kaufmann, M. Platzner, in: 2014 IEEE Intl. Conf. on Evolvable Systems (ICES), 2014, pp. 31–37.

EMG-basierte simultane und proportionale Online-Steuerung einer virtuellen Prothese
F. König, EMG-Basierte Simultane Und Proportionale Online-Steuerung Einer Virtuellen Prothese, Paderborn University, 2014.

Hardware Acceleration of Mechatronic Controllers on a Zynq Platform FPGA
B. Koch, Hardware Acceleration of Mechatronic Controllers on a Zynq Platform FPGA, Paderborn University, 2014.

Advanced AES-key recovery from decayed RAM using multi-threading and FPGAs
R. Mittendorf, Advanced AES-Key Recovery from Decayed RAM Using Multi-Threading and FPGAs, Paderborn University, 2014.

The Xilinx Zynq Architecture as a Platform for Reconfigurable Heterogeneous Multi-Cores
C. Rüthing, The Xilinx Zynq Architecture as a Platform for Reconfigurable Heterogeneous Multi-Cores, Paderborn University, 2014.

Parallel Monte-Carlo Tree Search for HPC Systems and its Application to Computer Go
L. Schäfers, Parallel Monte-Carlo Tree Search for HPC Systems and Its Application to Computer Go, Logos Verlag Berlin GmbH, Berlin, 2014.

Optimizing the Generator Start-up Sequence After a Power System Blackout
C. Shen, P. Kaufmann, M. Braun, in: IEEE Power and Energy Society General Meeting (IEEE GM), 2014.

A New Distribution Network Reconfiguration and Restoration Path Selection Algorithm
C. Shen, P. Kaufmann, M. Braun, in: Power Systems Computation Conference (PSCC), IEEE, 2014.

Multithreaded Parallelization of Mechatronic Controllers on a Zynq Platform FPGA
S. Surmund, Multithreaded Parallelization of Mechatronic Controllers on a Zynq Platform FPGA, Paderborn University, 2014.

Applications of Evolutionary Computation - 17th European Conference, EvoApplications
A. I. Esparcia-Alc\rquote azar, A.E. Eiben, A. Agapitos, A. Sim\'7eoes, A. G.B. Tettamanzi, A. Della Cioppa, A. M. Mora, C. Cotta, E. Tarantino, E. Haasdijk, F. Divina, F. Fern\rquote andez de Vega, G. Squillero, I. De Falco, J. Ignacio Hidalgo, K. Sim, K. Glette, M. Zhang, N. Urquhart, P. Burelli, P. Kaufmann, P. Po\'76 s\rquote k, R. Schaefer, R. Drechsler, S. Antipolis, S. Cagnoni, T. Thanh Nguyen, W. S. Bush (editors), Applications of Evolutionary Computation - 17th European Conference, EvoApplications, Springer, Granada, Spain, 2014.

Analytic reliability evaluation for fault-tolerant circuit structures on FPGAs
J. Anwer, M. Platzner, in: IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), IEEE, 2014, pp. 177–184.

Fast process variation analysis in nano-scaled technologies using column-wise sparse parameter selection
H. Ghasemzadeh Mohammadi, P.-E. Gaillardon, M. Yazdani, G. De Micheli, in: 2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), IEEE, 2014, pp. 163–168.

Common Fate Graph Patterns in Monte Carlo Tree Search for Computer Go
T. Graf, M. Platzner, in: 2014 IEEE Conference on Computational Intelligence and Games, 2014, pp. 1–8.

Verschiebungen an der Grenze zwischen Hardware und Software
M. Platzner, C. Plessl, in: J. Künsemöller, N.O. Eke, L. Foit, T. Kaerlein (Eds.), Logiken strukturbildender Prozesse: Automatismen, Wilhelm Fink, Paderborn, 2014, pp. 123–144.

Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer
T. Kenter, G.F. Vaz, C. Plessl, in: Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC), Springer International Publishing, Cham, 2014, pp. 144–155.

Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators
A. Agne, H. Hangmann, M. Happe, M. Platzner, C. Plessl, Microprocessors and Microsystems 38 (2014) 911–919.

Reconstructing AES Key Schedules from Decayed Memory with FPGAs
H. Riebler, T. Kenter, C. Plessl, C. Sorge, in: Proceedings of Field-Programmable Custom Computing Machines (FCCM), IEEE, 2014, pp. 222–229.

Self-awareness as a Model for Designing and Operating Heterogeneous Multicores
A. Agne, M. Happe, A. Lösch, C. Plessl, M. Platzner, ACM Transactions on Reconfigurable Technology and Systems (TRETS) 7 (2014).

ReconOS - An Operating System Approach for Reconfigurable Computing
A. Agne, M. Happe, A. Keller, E. Lübbers, B. Plattner, M. Platzner, C. Plessl, IEEE Micro 34 (2014) 60–71.

Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach
G. C. Durelli, M. Pogliani, A. Miele, C. Plessl, H. Riebler, G.F. Vaz, M. D. Santambrogio, C. Bolchini, in: Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA), IEEE, 2014, pp. 142–149.

Deferring Accelerator Offloading Decisions to Application Runtime
G.F. Vaz, H. Riebler, T. Kenter, C. Plessl, in: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2014, pp. 1–8.

Kernel-Centric Acceleration of High Accuracy Stereo-Matching
T. Kenter, H. Schmitz, C. Plessl, in: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2014, pp. 1–8.

SAVE: Towards efficient resource management in heterogeneous system architectures
G. C. Durelli, M. Copolla, K. Djafarian, G. Koranaros, A. Miele, M. Paolino, O. Pell, C. Plessl, M. D. Santambrogio, C. Bolchini, in: Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC), Springer, 2014.

Accelerating Finite Difference Time Domain Simulations with Reconfigurable Dataflow Computers
H. Giefers, C. Plessl, J. Förstner, ACM SIGARCH Computer Architecture News 41 (2014) 65–70.

Adapting Hardware Systems by Means of Multi-Objective Evolution
P. Kaufmann, Adapting Hardware Systems by Means of Multi-Objective Evolution, Logos Verlag Berlin GmbH, Berlin, 2013.

FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm
S. Kasap, S. Redif, in: Proc. IEEE Signal Processing and Communications Conf. (SUI), IEEE, 2013.

Novel Field-Programmable Gate Array Architecture for Computing the Eigenvalue Decomposition of Para-Hermitian Polynomial Matrices
S. Kasap, S. Redif, IEEE Trans. on Very Large Scale Integration (VLSI) Systems 22 (2013) 522–536.

Performance and thermal management on self-adaptive hybrid multi-cores
M. Happe, Performance and Thermal Management on Self-Adaptive Hybrid Multi-Cores, Logos Verlag Berlin GmbH, Berlin, 2013.

A Self-adaptive Heterogeneous Multi-core Architecture for Embedded Real-time Video Object Tracking
M. Happe, E. Lübbers, M. Platzner, International Journal of Real-Time Image Processing 8 (2013) 95–110.

Dynamic reliability management: Reconfiguring reliability-levels of hardware designs at runtime
J. Anwer, S. Meisner, M. Platzner, in: Reconfigurable Computing and FPGAs (ReConFig), 2013 International Conference On, 2013, pp. 1–6.

Beschleunigung von Tiefenberechnung aus Stereobildern durch FPGA-basierte Datenflussrechner
C. Bick, Beschleunigung von Tiefenberechnung Aus Stereobildern Durch FPGA-Basierte Datenflussrechner, Paderborn University, 2013.

Improving transient state myoelectric signal recognition in hand movement classification using gyroscopes
A. Boschmann, B. Nofen, M. Platzner, in: Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC), 2013.

Reducing the limb position effect in pattern recognition based myoelectric control using a high density electrode array
A. Boschmann, M. Platzner, in: Proc. IEEE ISSNIP Biosignals and Biorobotics Conference (BRC), 2013.

Investigating Evolvable Hardware Classification for the BioSleeve Electromyographic Interface
K. Glette, P. Kaufmann, C. Assad, M. Wolf, in: IEEE Intl. Conf. on Evolvable Systems (ICES), Springer, 2013, pp. 1–1.

Adapting Hardware Systems by Means of Multi-Objective Evolution
P. Kaufmann, Adapting Hardware Systems by Means of Multi-Objective Evolution, Logos Verlag, Berlin, 2013.

Classification of Electromyographic Signals: Comparing Evolvable Hardware to Conventional Classifiers
P. Kaufmann, K. Glette, T. Gruber, M. Platzner, J. Torresen, B. Sick, IEEE Transactions on Evolutionary Computation 17 (2013) 46–63.