Walder, Herbert, and Marco Platzner. “Online Scheduling for Block-Partitioned Reconfigurable Devices.”10.1109/date.2003.1253622__Proceedings Design, Automation and Test in Europe Conference (DATE), IEEE CS Press, 2003, pp. 290–95, doi:10.1109/date.2003.1253622.

Walder, Herbert, et al. “Fast Online Task Placement on FPGAs: Free Space Partitioning and 2D-Hashing.”10.1109/ipdps.2003.1213329__Proceedings International Parallel and Distributed Processing Symposium, IEEE CS Press, 2003, doi:10.1109/ipdps.2003.1213329.

Walder, Herbert, and Marco Platzner. “Reconfigurable Hardware Operating Systems: From Design Concepts to Realizations.” Proceedings of the 3rd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2003, pp. 284–87.

Steiger, Christoph, et al. “Heuristics for Online Scheduling Real-Time Tasks to Partially Reconfigurable Devices.”10.1007/978-3-540-45234-8_56__Proceedings of the 13th International Conference on Field Programmable Logic and Applications (FPL), Springer, 2003, pp. 575–84, doi:10.1007/978-3-540-45234-8_56.

Steiger, Christoph, et al. “Online Scheduling and Placement of Real-Time Tasks to Partially Reconfigurable Devices.”10.1109/real.2003.1253269__Proceedings 24th IEEE International Real-Time Systems Symposium (RTSS), IEEE CS Press, 2003, pp. 252–235, doi:10.1109/real.2003.1253269.

Plessl, Christian, et al. “Reconfigurable Hardware in Wearable Computing Nodes.”10.1109/ISWC.2002.1167250__Proc. Int. Symp. on Wearable Computers (ISWC), IEEE Computer Society, 2002, pp. 215–22, doi:10.1109/ISWC.2002.1167250.

Dyer, Matthias, et al. “Partially Reconfigurable Cores for Xilinx Virtex.”10.1007/3-540-46117-5__Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), vol. 2438, Springer, 2002, pp. 292–301, doi:10.1007/3-540-46117-5.

Plessl, Christian, and Marco Platzner. “Custom Computing Machines for the Set Covering Problem.”10.1109/FPGA.2002.1106671__Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), IEEE Computer Society, 2002, pp. 163–72, doi:10.1109/FPGA.2002.1106671.

Eisenring, Michael, and Marco Platzner. “A Framework for Run-Time Reconfigurable Systems.”10.1023/a:1013627403946__The Journal of Supercomputing, vol. 21, no. 2, Kluwer Academic Publishers, 2002, pp. 145–59, doi:10.1023/a:1013627403946.

Walder, Herbert, and Marco Platzner. “Non-Preemptive Multitasking on FPGAs: Task Placement and Footprint Transform.” Proceedings of the 2nd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2002, pp. 24–30.

Plessl, Christian, and Marco Platzner. “Instance-Specific Accelerators for Minimum Covering.” Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2001, pp. 85–91.

Enzler, Rolf, et al. “Reconfigurable Processors for Handhelds and Wearables: Application Analysis.”10.1117/12.434376__Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III, vol. 4525, 2001, pp. 135–46, doi:10.1117/12.434376.

Mencer, Oskar, et al. “Object-Oriented Domain Specific Compilers for Programming FPGAs.”10.1109/92.920835__IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 9, no. 1, 2001, pp. 205–10, doi:10.1109/92.920835.

Enzler, Rolf, and Marco Platzner. Dynamically Reconfigurable Processors. TELEMATIK, Zeitschrift des Telematik-Ingebieur-Verbandes 7(1), 2001.

Platzner, Marco. “Reconfigurable Accelerators for Combinatorial Problems.”10.1109/2.839322__Computer, vol. 33, no. 4, Institute of Electrical and Electronics Engineers (IEEE), 2000, pp. 58–60, doi:10.1109/2.839322.

Eisenring, Michael, and Marco Platzner. “Synthesis of Interfaces and Communication in Reconfigurable Embedded Systems.”10.1049/ip-cdt:20000496__IEE Proceedings -- Computers &; Digital Techniques, vol. 147, IET, 2000, pp. 159–65, doi:10.1049/ip-cdt:20000496.

Platzner, Marco, et al. “Toward Embedded Qualitative Simulation: A Specialized Computer Architecture for QSim.”10.1109/5254.850829__IEEE Intelligent Systems, vol. 15, no. 2, Institute of Electrical \'26; Electronics Engineers (IEEE), 2000, pp. 62–68, doi:10.1109/5254.850829.

Eisenring, Michael H., and Marco Platzner. “An Implementation Framework for Run-Time Reconfigurable Systems.” Proceedings of the 2nd International Workshop on Engineering of Reconfigurable Hardware/Software Objects (ENREGLE), CSREA Press, 2000, pp. 151–57.

Eisenring, Michael, and Marco Platzner. “Optimization of Run-Time Reconfigurable Embedded Systems.” Proceedings of the 10th International Workshop on Field Programmable Logic and Applications (FPL), Springer, 2000, pp. 565–74.

Mencer, Oskar, and Marco Platzner. “Dynamic Circuit Generation for Boolean Satisfiability in an Object-Oriented Design Environment.”10.1109/hicss.1999.772883__Proceedings of the 32nd Annual Hawaii International Conference on Systems Sciences (HICSS-32), IEEE CS Press, 1999, doi:10.1109/hicss.1999.772883.

Eisenring, Michael, et al. “Communication Synthesis for Reconfigurable Embedded Systems.”10.1007/978-3-540-48302-1_21__Proceedings of the 9th International Workshop on Field Programmable Logic and Applications (FPL), vol. 1673, Springer, 1999, pp. 205–14, doi:10.1007/978-3-540-48302-1_21.

Platzner, Marco. “Reconfigurable Computer Architectures.” E&;i Elektrotechnik Und Informationstechnik, vol. 115, Springer, 1998, pp. 143–48.

Platzner, Marco, and Bernhard Rinner. “Design and Implementation of a Parallel Constraint Satisfaction Algorithm.” International Journal of Computers &; Their Applications, vol. 5, ISCA, 1998, pp. 106–16.

Platzner, Marco, et al. A Distributed Computer Architecture for Fast Qualitative Simulation . Texas Instruments, The Elite Yearbook 1997 - Digital Signal Processing Solutions from Europe’s leading Universities, 1998, pp. 106–07.

Platzner, Marco, and Giovanni De Micheli. “Acceleration of Satisfiability Algorithms by Reconfigurable Hardware.”10.1007/bfb0055234__Proceedings of the 8th International Workshop on Field Programmable Logic and Applications (FPL) , Springer , 1998, pp. 69–78, doi:10.1007/bfb0055234.

Platzner, Marco, et al. “A Computer Architecture to Support Qualitative Simulation in Industrial Applications.” E &; i Elektrotechnik Und Informationstechnik, vol. 114, Springer, 1997, pp. 13–18.

Platzner, Marco, et al. “Parallel Qualitative Simulation.”10.1016/s0928-4869(97)00008-6__Simulation Practice and Theory, vol. 5, no. 7–8, Elsevier, 1997, pp. 623–38, doi:10.1016/s0928-4869(97)00008-6.

Platzner, Marco, and Liliane Peters. “Fast Signature Segmentation on a Multi-DSP Architecture.” Proceedings of the SPIE: Conference on Parallel and Distributed Methods for Image Processing, vol. 3166, 1997.

Röwekamp, Thomas, et al. “Specialized Architectures for Optical Flow Computation: A Performance Comparison of ASIC, DSP, and Multi-DSP.” Proceedings of the 8th International Conference on Signal Processing Applications &; Technology (ICSPAT), 1997, pp. 829–33.

Lind, Erich, et al. “A Multi-DSP System with Dynamically Reconfigurable Processors.” Proceedings of the 7th International Conference on Signal Processing Applications &; Technology (ICSPAT), 1996.

Platzner, Marco, et al. “Exploiting Parallelism in Constraint Satisfaction for Qualitative Simulation.” J.UCS Journal of Universal Computer Science, vol. 12, Springer, 1995, pp. 811–20.

Platzner, Marco, et al. “A Distributed Computer Architecture for Qualitative Simulation Based on a Multi-DSP and FPGAs.” Proceedings of the 3rd Euromicro Workshop on Parallel and Distributed Processing , IEEE CS Press, 1995, pp. 311–18.

Brenner, Eugen, et al. “High-Performance Simulators Based on Multi-TM0.” Proceedings of the 5th Annual Texas Instruments TM0 Educators Conference, 1995.

Friedl, Gerald, et al. “A Special-Purpose Coprocessor for Qualitative Simulation.” Proceedings of the EURO-PAR’95 International Conference on Parallel Processing, Springer International Publishing, 1995, pp. 695–98.

Platzner, Marco, et al. “Parallel Qualitative Simulation.” Proceedings of the EUROSIM Congress, Elsevier, 1995, pp. 231–36.

Platzner, Marco, and Bernhard Rinner. “Improving Performance of the Qualitative Simulator QSIM - Design and Implementation of a Specialized Computer Architecture.” Proceedings of the PDCS International Conference on Parallel and Distributed Computing Systems, ISCA, 1995, pp. 494–501.

Platzner, Marco, and Bernhard Rinner. “High-Performance Qualitative Simulation on a Multi-DSP Architecture.” Proceedings of the 6th International Conference on Signal Processing Applications &; Technology (ICSPAT), 1995.

Hranitzky, Robert, and Marco Platzner. “Design and Implementation of Adaptive Digital Filters on a Multi-TM0 System.” Proceedings of the 6th International Conference on Signal Processing Applications &; Technology (ICSPAT), 1995.

Platzner, Marco, et al. “Experimental Evaluation of Multi-DSP Architectures in High Performance Applications.” Proceedings of the 7th Mediterranean Electrotechnical Conference, IEEE Press, 1994.

Platzner, Marco, and Christian Steger. “Erfahrungen mit einer Multi-Signalprozessorarchitektur (TM0).” Mikroelektronik, 1993.

Platzner, Marco, et al. “Performance Measurements on a Multi-DSP Architecture with TM0.” Proceedings of the 4th International Conference on Signal Processing Applications &; Technology (ICSPAT), DSP Associates, 1993.

Ginthör, Robert, et al. “Experimental Results to Interprocessor Communication in Distributed Transputer-Systems.” Proceedings of the 1st Austrian-Hungarian Workshop on Transputer Applications, 1992, pp. 45–54.