Graf, T., Schaefers, L., &; Platzner, M. (2014). On Semeai Detection in Monte-Carlo Go. In Proc. Conf. on Computers and Games (CG) (pp. 14–25). Switzerland: Springer.https://doi.org/10.1007/978-3-319-09165-5_2 

Wiersema, T., Drzevitzky, S., &; Platzner, M. (2014). Memory Security in Reconfigurable Computers: Combining Formal Verification with Monitoring. In Proceedings of the International Conference on Field-Programmable Technology (FPT) (pp. 167–174).https://doi.org/10.1109/FPT.2014.7082771 

Jakobs, M.-C., Platzner, M., Wiersema, T., &; Wehrheim, H. (2014). Integrating Software and Hardware Verification. In E. Albert &; E. Sekerinski (Eds.), Proceedings of the 11th International Conference on Integrated Formal Methods (iFM) (pp. 307–322).https://doi.org/10.1007/978-3-319-10181-1_19 

Wiersema, T., Bockhorn, A., &; Platzner, M. (2014). Embedding FPGA Overlays into Configurable Systems-on-Chip: ReconOS meets ZUMA. In Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig) (pp. 1–6).https://doi.org/10.1109/ReConFig.2014.7032514 

Schaefers, L., &; Platzner, M. (2014). A Novel Technique and its Application to Computer Go. IEEE Transactions on Computational Intelligence and AI in Games, 6(3), 361–374.https://doi.org/10.1109/TCIAIG.2014.2346997 

Giefers, H., &; Platzner, M. (2014). An FPGA-based Reconfigurable Mesh Many-Core. IEEE Transactions on Computers, 63(12), 2919–2932.https://doi.org/10.1109/TC.2013.174 

Anwer, J., Platzner, M., &; Meisner, S. (2014). FPGA Redundancy Configurations: An Automated Design Space Exploration. In Reconfigurable Architectures Workshop (RAW).https://doi.org/10.1109/IPDPSW.2014.37 

Bockhorn, A. (2014). Echtzeit Klassifikation von sEMG Signalen mit einem low-cost DSP Evaluation Board. Paderborn University.

Boschmann, A., &; Platzner, M. (2014). A computer vision-based approach to high density EMG pattern recognition using structural similarity. In Proc. MyoElectric Controls Symposium (MEC).

Boschmann, A., &; Platzner, M. (2014). Towards robust HD EMG pattern recognition: Reducing electrode displacement effect using structural similarity. In Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC).

Brand, M. (2014). A Generalized Loop Accelerator Implemented as a Coarse-Grained Array. Paderborn University.

Damschen, M. (2014). Easy-to-use-on-the-fly binary program acceleration on many-cores. Paderborn University.

Glette, K., &; Kaufmann, P. (2014). Lookup Table Partial Reconfiguration for an Evolvable Hardware Classifier System. In IEEE Congress on Evolutionary Computation (CEC).

Hagedorn, C. (2014). Entwicklung einer codegrößenoptimierten Softwarebibliothek für 8-Bit Mikrocontroller in netzunabhängigen Notleuchten. Paderborn University.

Ho, N., Kaufmann, P., &; Platzner, M. (2014). A hardware/software infrastructure for performance monitoring on LEON3 multicore platforms. In 24th Intl. Conf. on Field Programmable Logic and Applications (FPL) (pp. 1–4).https://doi.org/10.1109/FPL.2014.6927437 

Ho, N., Kaufmann, P., &; Platzner, M. (2014). Towards self-adaptive caches: A run-time reconfigurable multi-core infrastructure. In 2014 IEEE Intl. Conf. on Evolvable Systems (ICES) (pp. 31–37).https://doi.org/10.1109/ICES.2014.7008719 

König, F. (2014). EMG-basierte simultane und proportionale Online-Steuerung einer virtuellen Prothese. Paderborn University.

Koch, B. (2014). Hardware Acceleration of Mechatronic Controllers on a Zynq Platform FPGA. Paderborn University.

Mittendorf, R. (2014). Advanced AES-key recovery from decayed RAM using multi-threading and FPGAs. Paderborn University.

Rüthing, C. (2014). The Xilinx Zynq Architecture as a Platform for Reconfigurable Heterogeneous Multi-Cores. Paderborn University.