B. Runde, A Token-Ring Network-On-Chip for Message Passing in ReconOS. Paderborn University, 2010.

T. Wiersema, Scheduling Support for Heterogeneous Hardware Accelerators under Linux. Paderborn University, 2010.

M. Platzner, J. Teich, and N. Wehn, Eds., Dynamically Reconfigurable Systems: Architectures, Design Methods and Applications. Springer-Verlag GmbH, 2010.

M. Khatir, H. Ghasemzadeh Mohammadi, and A. Ejlali, “Sub-threshold charge recovery circuits,” in Computer Design (ICCD), 2010 IEEE International Conference on, 2010, pp. 138–144.

H. Giefers and M. Platzner, “A Triple Hybrid Interconnect for Many-Cores: Reconfigurable Mesh, NoC and Barrier,” in Proceedings of the 20th International Conference on Field Programmable Logic and Applications (FPL), 2010.

W. Schäfer et al., “Engineering Self-Coordinating Software Intensive Systems,” in Proceedings of the Foundations of Software Engineering (FSE) and NITR &; D/SPD Working Conference on the Future of Software Engineering Research (FoSER), 2010, pp. 321–324.

H. Giefers and M. Platzner, “A Self-Reconfigurable Lightweight Interconnect for Scalable Processor Fabrics,” in Proceedings of the 10th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2010.

E. Lübbers, M. Platzner, C. Plessl, A. Keller, and B. Plattner, “Towards Adaptive Networking for Embedded Devices based on Reconfigurable Hardware,” in Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2010, pp. 225–231.

M. Grad and C. Plessl, “Pruning the Design Space for Just-In-Time Processor Customization,”10.1109/ReConFig.2010.19__in Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), 2010, pp. 67–72, doi:10.1109/ReConFig.2010.19 .

M. Grad and C. Plessl, “An Open Source Circuit Library with Benchmarking Facilities,” in Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2010, pp. 144–150.

D. Andrews and C. Plessl, “Configurable Processor Architectures: History and Trends,” in Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2010, p. 165.

T. P. Plaks et al., Eds., Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press, 2010.

T. Beisel, M. Niekamp, and C. Plessl, “Using Shared Library Interposing for Transparent Acceleration in Systems with Heterogeneous Hardware Accelerators,”10.1109/ASAP.2010.5540798__in Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), 2010, pp. 65–72, doi:10.1109/ASAP.2010.5540798 .

A. Keller, B. Plattner, E. Lübbers, M. Platzner, and C. Plessl, “Reconfigurable Nodes for Future Networks,”10.1109/GLOCOMW.2010.5700341__in Proc. IEEE Globecom Workshop on Network of the Future (FutureNet), 2010, pp. 372–376, doi:10.1109/GLOCOMW.2010.5700341 .

T. Kenter, M. Platzner, C. Plessl, and M. Kauschke, “Performance Estimation for the Exploration of CPU-Accelerator Architectures,” in Proc. Workshop on Architectural Research Prototyping (WARP), International Symposium on Computer Architecture (ISCA), 2010.

A. Boschmann, P. Kaufmann, M. Platzner, and M. Winkler, “Towards multi-movement hand prostheses: Combining adaptive classification with high precision sockets,” in Proc. Technically Assisted Rehabilitation (TAR), 2009.

A. Kostin, Evolvable Robot Controller. Paderborn University, 2009.

E. Lübbers and M. Platzner, “ReconOS: Multithreaded Programming for Reconfigurable Computers,” ACM Transactions on Embedded Computing Systems, vol. 9, no. 1, pp. 8:1-8:33, 2009.

M. Tofall, Compiler for a Custom Instruction Set CPU. Paderborn University, 2009.

A. Warkentin, Coarse-grained CGP Model using Xilinx Virte DSE Functional Units. Paderborn University, 2009.