SIRA: Scaled-Integer Range Analysis for Optimizing FPGA Dataflow Neural Network Accelerators
Y. Umuroglu, C. Berganski, F. Jentzsch, M. Danilowicz, T. Kryjak, C. Bezaitis, M. Sjalander, I. Colbert, T. Preusser, J. Petri-Koenig, M. Blott, ACM Transactions on Reconfigurable Technology and Systems (n.d.).

A Computation of the Ninth Dedekind Number Using FPGA Supercomputing
L. Van Hirtum, P. De Causmaecker, J. Goemaere, T. Kenter, H. Riebler, M. Lass, C. Plessl, ACM Transactions on Reconfigurable Technology and Systems 17 (2024) 1–28.

Multi-FPGA Designs and Scaling of HPC Challenge Benchmarks via MPI and Circuit-Switched Inter-FPGA Networks
M. Meyer, T. Kenter, C. Plessl, ACM Transactions on Reconfigurable Technology and Systems (2023).

The Strong Scaling Advantage of FPGAs in HPC for N-body Simulations
J. Menzel, C. Plessl, T. Kenter, ACM Transactions on Reconfigurable Technology and Systems 15 (2021) 1–30.

Design of Distributed Reconfigurable Robotics Systems with ReconROS
C. Lienen, M. Platzner, ACM Transactions on Reconfigurable Technology and Systems (2021) 1–20.

Efficient Branch and Bound on FPGAs Using Work Stealing and Instance-Specific Designs
H. Riebler, M. Lass, R. Mittendorf, T. Löcke, C. Plessl, ACM Transactions on Reconfigurable Technology and Systems (TRETS) 10 (2017) 24:1-24:23.