SORCERI: Streaming Overlay Acceleration for Highly Contracted Electron Repulsion Integral Computations in Quantum Chemistry
P. Stachura, X. Wu, C. Plessl, Z. Fang, in: Proceedings of the 2026 ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA ’26), Association for Computing Machinery, New York, NY, USA, 2026, pp. 224–234.

Evaluating oneAPI I/O Pipes in a Case Study of Scaling a SYCL Jacobi Solver to multiple FPGAs
C. Alt, C. Plessl, T. Kenter, in: Proceedings of the 13th International Workshop on OpenCL and SYCL, Association for Computing Machinery, New York, NY, USA, 2025.

Otus Supercomputer
S. Ehtesabi, M. Hossain, T. Kenter, A. Krawinkel, L. Ostermann, C. Plessl, H. Riebler, S. Rohde, R. Schade, M. Schwarz, J. Simon, N. Winnwa, A. Wiens, X. Wu, Otus Supercomputer, Paderborn Center for Parallel Computing (P), Paderborn, 2025.

Noctua 2 Supercomputer
C. Bauer, T. Kenter, M. Lass, L. Mazur, M. Meyer, H. Nitsche, H. Riebler, R. Schade, M. Schwarz, N. Winnwa, A. Wiens, X. Wu, C. Plessl, J. Simon, Journal of Large-Scale Research Facilities 9 (2024).

Hardware Trojans in Reconfigurable Computing
Q.A. Ahmed, Hardware Trojans in Reconfigurable Computing,  Paderborn University, Paderborn, Germany, Paderborn, 2022.

Evaluating FPGA Accelerator Performance with a Parameterized OpenCL Adaptation of Selected Benchmarks of the HPCChallenge Benchmark Suite
M. Meyer, T. Kenter, C. Plessl, in: 2020 IEEE/ACM International Workshop on Heterogeneous High-Performance Reconfigurable Computing (RC), 2020.

Zynq-based acceleration of robust high density myoelectric signal processing
A. Boschmann, A. Agne, G. Thombansen, L.M. Witschen, F. Kraus, M. Platzner, Journal of Parallel and Distributed Computing 123 (2019) 77–89.

Accelerating Molecular Dynamic Simulations by Offloading Fast Fourier Transformations to FPGA
A. Ramaswami, Accelerating Molecular Dynamic Simulations by Offloading Fast Fourier Transformations to FPGA, Universität Paderborn, 2018.

Microarchitectural optimization by means of reconfigurable and evolvable cache mappings
N. Ho, A.F. Ahmed, P. Kaufmann, M. Platzner, in: Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS), 2015, pp. 1–7.

Dynamic reliability management: Reconfiguring reliability-levels of hardware designs at runtime
J. Anwer, S. Meisner, M. Platzner, in: Reconfigurable Computing and FPGAs (ReConFig), 2013 International Conference On, 2013, pp. 1–6.

System-level performance evaluation of reconfigurable processors
R. Enzler, C. Plessl, M. Platzner, Microprocessors and Microsystems 29 (2005) 63–73.

TKDM – A Reconfigurable Co-processor in a PC's Memory Slot
C. Plessl, M. Platzner, in: Proc. Int. Conf. on Field Programmable Technology (ICFPT), IEEE Computer Society, 2003, pp. 252–259.

Virtualizing Hardware with Multi-Context Reconfigurable Arrays
R. Enzler, C. Plessl, M. Platzner, in: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), Springer, 2003, pp. 151–160.