Amiri A, Tavana M, Arman H. An Integrated Fuzzy Analytic Network Process and Fuzzy Regression Method for Bitcoin Price Prediction. Internet of Things. 2024;25. doi:10.1016/j.iot.2023.101027
LibreCat: /record/53213
DOI: 10.1016/j.iot.2023.101027

Mahmoodi E, Fathi M, Tavana M, Ghobakhloo M, Ng AHC. Data-driven simulation-based decision support system for resource allocation in industry 4.0 and smart manufacturing. Journal of Manufacturing Systems. 2024;72:287-307. doi:10.1016/j.jmsy.2023.11.019
LibreCat: /record/53212
DOI: 10.1016/j.jmsy.2023.11.019

Schade R, Kenter T, Elgabarty H, Lass M, Kühne T, Plessl C. Breaking the exascale barrier for the electronic structure problem in ab-initio molecular dynamics. The International Journal of High Performance Computing Applications. Published online 2023. doi:10.1177/10943420231177631
LibreCat: /record/45361
DOI: 10.1177/10943420231177631

Sadeghi-Kohan S, Hellebrand S, Wunderlich H-J. Workload-Aware Periodic Interconnect BIST. IEEE Design &;Test. Published online 2023:1-1. doi:10.1109/mdat.2023.3298849
LibreCat: /record/46264
DOI: 10.1109/mdat.2023.3298849

Tavana M, Khalili Nasr A, Ahmadabadi AB, Amiri AS, Mina H. An interval multi-criteria decision-making model for evaluating blockchain-IoT technology in supply chain networks. Internet of Things. 2023;22. doi:10.1016/j.iot.2023.100786
LibreCat: /record/53220
DOI: 10.1016/j.iot.2023.100786

Ahmed QA. Hardware Trojans in Reconfigurable Computing.10.17619/UNIPB/1-1271__Paderborn University, Paderborn, Germany; 2022. doi:10.17619/UNIPB/1-1271
LibreCat: /record/29769
DOI: 10.17619/UNIPB/1-1271

Kontinen J, Meier A, Mahmood Y. A parameterized view on the complexity of dependence and independence logic. Journal of Logic and Computation. 2022;32(8):1624-1644. doi:10.1093/logcom/exac070
LibreCat: /record/45847
DOI: 10.1093/logcom/exac070

Schade R, Kenter T, Elgabarty H, et al. Towards electronic structure-based ab-initio molecular dynamics simulations with hundreds of millions of atoms. Parallel Computing. 2022;111. doi:10.1016/j.parco.2022.102920
LibreCat: /record/33684
DOI: 10.1016/j.parco.2022.102920

Wiersema T. Guaranteeing Properties of Reconfigurable Hardware Circuits with Proof-Carrying Hardware. Paderborn University; 2021.
LibreCat: /record/26746

Rodriguez A, Otero A, Platzner M, De la Torre E. Exploiting Hardware-Based Data-Parallel and Multithreading Models for Smart Edge Computing in Reconfigurable FPGAs. IEEE Transactions on Computers. Published online 2021:1-1. doi:10.1109/tc.2021.3107196
LibreCat: /record/30907
DOI: 10.1109/tc.2021.3107196

Jakobs M-C, Pauck F, Platzner M, Wehrheim H, Wiersema T. Software/Hardware Co-Verification for Custom Instruction Set Processors. IEEE Access. Published online 2021. doi:10.1109/ACCESS.2021.3131213
LibreCat: /record/27841
DOI: 10.1109/ACCESS.2021.3131213

Witschen LM, Wiersema T, Platzner M. Proof-carrying Approximate Circuits. IEEE Transactions On Very Large Scale Integration Systems. 2020;28(9):2084-2088. doi:10.1109/TVLSI.2020.3008061
LibreCat: /record/17358
DOI: 10.1109/TVLSI.2020.3008061

Mahmood Y, Meier A, Schmidt J. Parameterized complexity of abduction in Schaefer’s framework. Journal of Logic and Computation. 2020;31(1):266-296. doi:10.1093/logcom/exaa079
LibreCat: /record/45845
DOI: 10.1093/logcom/exaa079

Jentzsch FP. Enforcing IP Core Connection Properties with Verifiable Security Monitors. Universität Paderborn; 2018.
LibreCat: /record/1097

Ho N, Kaufmann P, Platzner M. Evolvable caches: Optimization of reconfigurable cache mappings for a LEON3/Linux-based multi-core processor. In: 2017 International Conference on Field Programmable Technology (ICFPT). ; 2017:215-218. doi:10.1109/FPT.2017.8280144
LibreCat: /record/10676
DOI: 10.1109/FPT.2017.8280144

Guettatfi Z, Hübner P, Platzner M, Rinner B. Computational self-awareness as design approach for visual sensor nodes. In: 12th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC). ; 2017:1-8. doi:10.1109/ReCoSoC.2017.8016147
LibreCat: /record/10780
DOI: 10.1109/ReCoSoC.2017.8016147

Boschmann A, Agne A, Witschen LM, Thombansen G, Kraus F, Platzner M. FPGA-based acceleration of high density myoelectric signal processing. In: 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE; 2016. doi:10.1109/reconfig.2015.7393312
LibreCat: /record/15873
DOI: 10.1109/reconfig.2015.7393312

Guettatfi Z, Kermia O, Khouas A. Over effective hard real-time hardware tasks scheduling and allocation. In: 25th International Conference on Field Programmable Logic and Applications (FPL). Imperial College; 2015. doi:10.1109/FPL.2015.7293994
LibreCat: /record/10779
DOI: 10.1109/FPL.2015.7293994

Vidor F, Meyers T, Hilleringmann U. Flexible Electronics: Integration Processes for Organic and Inorganic Semiconductor-Based Thin-Film Transistors. Electronics. 2015;4(3):480-506. doi:10.3390/electronics4030480
LibreCat: /record/39479
DOI: 10.3390/electronics4030480

Ho N, Kaufmann P, Platzner M. A hardware/software infrastructure for performance monitoring on LEON3 multicore platforms. In: 24th Intl. Conf. on Field Programmable Logic and Applications (FPL). ; 2014:1-4. doi:10.1109/FPL.2014.6927437
LibreCat: /record/10674
DOI: 10.1109/FPL.2014.6927437

Alizadeh B, Behnam P, Sadeghi-Kohan S. A Scalable Formal Debugging Approach with Auto-Correction Capability based on Static Slicing and Dynamic Ranking for RTL Datapath Designs. IEEE Transactions on Computers. Published online 2014:1-1. doi:10.1109/tc.2014.2329687
LibreCat: /record/46266
DOI: 10.1109/tc.2014.2329687

Anwer J, Meisner S, Platzner M. Dynamic reliability management: Reconfiguring reliability-levels of hardware designs at runtime. In: Reconfigurable Computing and FPGAs (ReConFig), 2013 International Conference On. ; 2013:1-6. doi:10.1109/ReConFig.2013.6732280
LibreCat: /record/10620
DOI: 10.1109/ReConFig.2013.6732280

Xie T, Müller W, Letombe F. Mutation-Analysis Driven Functional Verification of a Soft Microprocessor. In: Proceedings of SO. IEEE; 2012. doi:10.1109/SOCC.2012.6398362
LibreCat: /record/36994
DOI: 10.1109/SOCC.2012.6398362

Oliveira MFS, Zabel H, Müller W. Assertion-Based Verification of RTOS Properties. In: Proceedings of DATE’10. IEEE; 2010. doi:10.1109/DATE.2010.5457130
LibreCat: /record/37009
DOI: 10.1109/DATE.2010.5457130

Klobedanz K, Kuznik C, Thuy A, Müller W. Timing Modeling and Analysis for AUTOSAR-Based Software Development - A Case Study. In: Proceedings of DATE’10, Dresden. IEEE; 2010. doi:10.1109/DATE.2010.5457125
LibreCat: /record/37011
DOI: 10.1109/DATE.2010.5457125

Becker M, Di Guglielmo G, Fummi F, Müller W, Pravadelli G, Xie T. RTOS-Aware Refinement for TLM2.0-based HW/SW Design. In: Proceedings of DATE’10. IEEE; 2010. doi:10.1109/DATE.2010.5456965
LibreCat: /record/37040
DOI: 10.1109/DATE.2010.5456965

Müller W, da S. Oliveira MF, Zabel H, Becker M. Verification of Real-Time Properties for Hardware-Dependant Software. In: Proceedings of HLD. IEEE; 2010.
LibreCat: /record/37053

Ecker W, Müller W, Dömer R. Hardware-dependent Software - Introduction and Overview. In: Ecker W, Müller W, Dömer R, eds. Hardware Dependent Software - Principles and Practice. Springer Verlag; 2009:1-14. doi:10.1007/978-1-4020-9436-1_1
LibreCat: /record/33814
DOI: 10.1007/978-1-4020-9436-1_1

Kaufmann P, Plessl C, Platzner M. EvoCaches: Application-specific Adaptation of Cache Mapping. In: Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS). IEEE Computer Society; 2009:11-18.
LibreCat: /record/2262

Kaufmann P, Platzner M. MOVES: A Modular Framework for Hardware Evolution. In: Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007). IEEE; 2007:447-454. doi:10.1109/ahs.2007.73
LibreCat: /record/6508
DOI: 10.1109/ahs.2007.73

Danne K, Mühlenbernd R, Platzner M. Server-based execution of periodic tasks on dynamically reconfigurable hardware. IET Computers Digital Techniques. 2007;1(4):295-302. doi:10.1049/iet-cdt:20060186
LibreCat: /record/10646
DOI: 10.1049/iet-cdt:20060186

Großmann J, Müller W. A Formal Behavioral Semantics for TestML. In: Proc. of ISOLA 06. ; 2006. doi:10.1109/ISoLA.2006.37
LibreCat: /record/38107
DOI: 10.1109/ISoLA.2006.37

Schattkowsky T, Müller W, Rettberg A. A Model-Based Approach for Executable Specification on Reconfigurable Hardware. In: Proceedings of DATE’05. IEEE; 2005. doi:10.1109/DATE.2005.20
LibreCat: /record/39029
DOI: 10.1109/DATE.2005.20

Schattkowsky T, Müller W. A UML Virtual Machine for Embedded Systems. In: Proceedings of ISNG 05. ; 2005.
LibreCat: /record/39030

Schattkowsky T, Müller W. Transformation of UML State Machines for Direct Execution. In: Proceedings of VL/HCC 05. ; 2005. doi:10.1109/VLHCC.2005.64
LibreCat: /record/39032
DOI: 10.1109/VLHCC.2005.64

Plessl C, Platzner M. Virtualization of Hardware – Introduction and Survey. In: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press; 2004:63-69.
LibreCat: /record/2415

Goser K, Hilleringmann U, Rueckert U, Schumacher K. VLSI technologies for artificial neural networks. IEEE Micro. 2002;9(6):28-44. doi:10.1109/40.42985
LibreCat: /record/39925
DOI: 10.1109/40.42985

Goser K, Hilleringmann U, Rueckert U, Schumacher K. VLSI technologies for artificial neural networks. IEEE Micro. 2002;9(6):28-44. doi:10.1109/40.42985
LibreCat: /record/39926
DOI: 10.1109/40.42985

Müller W, Ruf J, Hoffmann DW, Gerlach J, Kropf T, Rosenstiehl W. The Simulation Semantics of SystemC. In: Proceedings of the Design, Automation, and Test in Europe (DATE’01). IEEE; 2001. doi:10.1109/DATE.2001.915002
LibreCat: /record/39421
DOI: 10.1109/DATE.2001.915002

Dücker M, Geiger C, Hunstock R, Lehrenfeld G, Müller W. Visual-Textual Prototyping of 4D Scenes. In: Proceedings of the 1997 IEEE Symposium on Visual Languages. ; 1997. doi:10.1109/VL.1997.626601
LibreCat: /record/39505
DOI: 10.1109/VL.1997.626601

Griebel P, Lehrenfeld G, Müller W, Tahedl C, Uhr H. Integrating a Constraint Solver into a Real-Time Animation Environment. In: Proceedings of the 1996 IEEE Symposium on Visual Languages. ; 1996. doi:10.1109/VL.1996.545262
LibreCat: /record/39521
DOI: 10.1109/VL.1996.545262