Amiri, A., Tavana, M., &; Arman, H. (2024). An Integrated Fuzzy Analytic Network Process and Fuzzy Regression Method for Bitcoin Price Prediction. Internet of Things, 25, Article 101027.https://doi.org/10.1016/j.iot.2023.101027 
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Mahmoodi, E., Fathi, M., Tavana, M., Ghobakhloo, M., &; Ng, A. H. C. (2024). Data-driven simulation-based decision support system for resource allocation in industry 4.0 and smart manufacturing. Journal of Manufacturing Systems, 72, 287–307.https://doi.org/10.1016/j.jmsy.2023.11.019 
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Schade, R., Kenter, T., Elgabarty, H., Lass, M., Kühne, T., &; Plessl, C. (2023). Breaking the exascale barrier for the electronic structure problem in ab-initio molecular dynamics. The International Journal of High Performance Computing Applications, Article 109434202311776.https://doi.org/10.1177/10943420231177631 
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Sadeghi-Kohan, S., Hellebrand, S., &; Wunderlich, H.-J. (2023). Workload-Aware Periodic Interconnect BIST. IEEE Design &;Test, 1–1.https://doi.org/10.1109/mdat.2023.3298849 
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Tavana, M., Khalili Nasr, A., Ahmadabadi, A. B., Amiri, A. S., &; Mina, H. (2023). An interval multi-criteria decision-making model for evaluating blockchain-IoT technology in supply chain networks. Internet of Things, 22, Article 100786.https://doi.org/10.1016/j.iot.2023.100786 
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Ahmed, Q. A. (2022). Hardware Trojans in Reconfigurable Computing.https://doi.org/10.17619/UNIPB/1-1271__Paderborn University, Paderborn, Germany.https://doi.org/10.17619/UNIPB/1-1271 
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Kontinen, J., Meier, A., &; Mahmood, Y. (2022). A parameterized view on the complexity of dependence and independence logic. Journal of Logic and Computation, 32(8), 1624–1644.https://doi.org/10.1093/logcom/exac070 
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Schade, R., Kenter, T., Elgabarty, H., Lass, M., Schütt, O., Lazzaro, A., Pabst, H., Mohr, S., Hutter, J., Kühne, T., &; Plessl, C. (2022). Towards electronic structure-based ab-initio molecular dynamics simulations with hundreds of millions of atoms. Parallel Computing, 111, Article 102920.https://doi.org/10.1016/j.parco.2022.102920 
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Wiersema, T. (2021). Guaranteeing Properties of Reconfigurable Hardware Circuits with Proof-Carrying Hardware. Paderborn University.
LibreCat: /record/26746

Rodriguez, A., Otero, A., Platzner, M., &; De la Torre, E. (2021). Exploiting Hardware-Based Data-Parallel and Multithreading Models for Smart Edge Computing in Reconfigurable FPGAs. IEEE Transactions on Computers, 1–1.https://doi.org/10.1109/tc.2021.3107196 
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Jakobs, M.-C., Pauck, F., Platzner, M., Wehrheim, H., &; Wiersema, T. (2021). Software/Hardware Co-Verification for Custom Instruction Set Processors. IEEE Access.https://doi.org/10.1109/ACCESS.2021.3131213 
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Witschen, L. M., Wiersema, T., &; Platzner, M. (2020). Proof-carrying Approximate Circuits. IEEE Transactions On Very Large Scale Integration Systems, 28(9), 2084–2088.https://doi.org/10.1109/TVLSI.2020.3008061 
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Mahmood, Y., Meier, A., &; Schmidt, J. (2020). Parameterized complexity of abduction in Schaefer’s framework. Journal of Logic and Computation, 31(1), 266–296.https://doi.org/10.1093/logcom/exaa079 
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Jentzsch, F. P. (2018). Enforcing IP Core Connection Properties with Verifiable Security Monitors. Universität Paderborn.
LibreCat: /record/1097

Ho, N., Kaufmann, P., &; Platzner, M. (2017). Evolvable caches: Optimization of reconfigurable cache mappings for a LEON3/Linux-based multi-core processor. In 2017 International Conference on Field Programmable Technology (ICFPT) (pp. 215–218).https://doi.org/10.1109/FPT.2017.8280144 
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Guettatfi, Z., Hübner, P., Platzner, M., &; Rinner, B. (2017). Computational self-awareness as design approach for visual sensor nodes. In 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC) (pp. 1–8).https://doi.org/10.1109/ReCoSoC.2017.8016147 
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Boschmann, A., Agne, A., Witschen, L. M., Thombansen, G., Kraus, F., &; Platzner, M. (2016). FPGA-based acceleration of high density myoelectric signal processing. In 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig). Mexiko City, Mexiko: IEEE.https://doi.org/10.1109/reconfig.2015.7393312 
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Guettatfi, Z., Kermia, O., &; Khouas, A. (2015). Over effective hard real-time hardware tasks scheduling and allocation. In 25th International Conference on Field Programmable Logic and Applications (FPL). Imperial College.https://doi.org/10.1109/FPL.2015.7293994 
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Vidor, F., Meyers, T., &; Hilleringmann, U. (2015). Flexible Electronics: Integration Processes for Organic and Inorganic Semiconductor-Based Thin-Film Transistors. Electronics, 4(3), 480–506.https://doi.org/10.3390/electronics4030480 
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Ho, N., Kaufmann, P., &; Platzner, M. (2014). A hardware/software infrastructure for performance monitoring on LEON3 multicore platforms. In 24th Intl. Conf. on Field Programmable Logic and Applications (FPL) (pp. 1–4).https://doi.org/10.1109/FPL.2014.6927437 
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Alizadeh, B., Behnam, P., &; Sadeghi-Kohan, S. (2014). A Scalable Formal Debugging Approach with Auto-Correction Capability based on Static Slicing and Dynamic Ranking for RTL Datapath Designs. IEEE Transactions on Computers, 1–1.https://doi.org/10.1109/tc.2014.2329687 
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Anwer, J., Meisner, S., &; Platzner, M. (2013). Dynamic reliability management: Reconfiguring reliability-levels of hardware designs at runtime. In Reconfigurable Computing and FPGAs (ReConFig), 2013 International Conference on (pp. 1–6).https://doi.org/10.1109/ReConFig.2013.6732280 
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Xie, T., Müller, W., &; Letombe, F. (2012). Mutation-Analysis Driven Functional Verification of a Soft Microprocessor. Proceedings of SO.https://doi.org/10.1109/SOCC.2012.6398362 
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Oliveira, M. F. S., Zabel, H., &; Müller, W. (2010). Assertion-Based Verification of RTOS Properties. Proceedings of DATE’10. 2010 Design, Automation &; Test in Europe Conference &; Exhibition (DATE 2010), Dresden.https://doi.org/10.1109/DATE.2010.5457130 
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Klobedanz, K., Kuznik, C., Thuy, A., &; Müller, W. (2010). Timing Modeling and Analysis for AUTOSAR-Based Software Development - A Case Study. Proceedings of DATE’10, Dresden. 2010 Design, Automation &; Test in Europe Conference &; Exhibition (DATE 2010), Dresden.https://doi.org/10.1109/DATE.2010.5457125 
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DOI: 10.1109/DATE.2010.5457125

Becker, M., Di Guglielmo, G., Fummi, F., Müller, W., Pravadelli, G., &; Xie, T. (2010). RTOS-Aware Refinement for TLM2.0-based HW/SW Design. Proceedings of DATE’10. Design, Automation &; Test in Europe Conference &; Exhibition (DATE 2010), Dresden.https://doi.org/10.1109/DATE.2010.5456965 
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Müller, W., da S. Oliveira, M. F., Zabel, H., &; Becker, M. (2010). Verification of Real-Time Properties for Hardware-Dependant Software. Proceedings of HLD. IEEE International High Level Design Validation and Test Workshop (HLDVT), Anaheim, FL, USA.
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Ecker, W., Müller, W., &; Dömer, R. (2009). Hardware-dependent Software - Introduction and Overview. In W. Ecker, W. Müller, &; R. Dömer (Eds.), Hardware Dependent Software - Principles and Practice (pp. 1–14). Springer Verlag.https://doi.org/10.1007/978-1-4020-9436-1_1 
LibreCat: /record/33814
DOI: 10.1007/978-1-4020-9436-1_1

Kaufmann, P., Plessl, C., &; Platzner, M. (2009). EvoCaches: Application-specific Adaptation of Cache Mapping. Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS), 11–18.
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Kaufmann, P., &; Platzner, M. (2007). MOVES: A Modular Framework for Hardware Evolution. In Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007) (pp. 447–454). Edinburgh, UK: IEEE.https://doi.org/10.1109/ahs.2007.73 
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Danne, K., Mühlenbernd, R., &; Platzner, M. (2007). Server-based execution of periodic tasks on dynamically reconfigurable hardware. IET Computers Digital Techniques, 1(4), 295–302.https://doi.org/10.1049/iet-cdt:20060186 
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DOI: 10.1049/iet-cdt:20060186

Großmann, J., &; Müller, W. (2006). A Formal Behavioral Semantics for TestML. Proc. of ISOLA 06.https://doi.org/10.1109/ISoLA.2006.37 
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DOI: 10.1109/ISoLA.2006.37

Schattkowsky, T., Müller, W., &; Rettberg, A. (2005). A Model-Based Approach for Executable Specification on Reconfigurable Hardware. Proceedings of DATE’05.https://doi.org/10.1109/DATE.2005.20 
LibreCat: /record/39029
DOI: 10.1109/DATE.2005.20

Schattkowsky, T., &; Müller, W. (2005). A UML Virtual Machine for Embedded Systems. Proceedings of ISNG 05.
LibreCat: /record/39030

Schattkowsky, T., &; Müller, W. (2005). Transformation of UML State Machines for Direct Execution. Proceedings of VL/HCC 05.https://doi.org/10.1109/VLHCC.2005.64 
LibreCat: /record/39032
DOI: 10.1109/VLHCC.2005.64

Plessl, C., &; Platzner, M. (2004). Virtualization of Hardware – Introduction and Survey. In Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) (pp. 63–69). CSREA Press.
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Goser, K., Hilleringmann, U., Rueckert, U., &; Schumacher, K. (2002). VLSI technologies for artificial neural networks. IEEE Micro, 9(6), 28–44.https://doi.org/10.1109/40.42985 
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Goser, K., Hilleringmann, U., Rueckert, U., &; Schumacher, K. (2002). VLSI technologies for artificial neural networks. IEEE Micro, 9(6), 28–44.https://doi.org/10.1109/40.42985 
LibreCat: /record/39926
DOI: 10.1109/40.42985

Müller, W., Ruf, J., Hoffmann, D. W., Gerlach, J., Kropf, T., &; Rosenstiehl, W. (2001). The Simulation Semantics of SystemC. Proceedings of the Design, Automation, and Test in Europe (DATE’01).https://doi.org/10.1109/DATE.2001.915002__Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.https://doi.org/10.1109/DATE.2001.915002 
LibreCat: /record/39421
DOI: 10.1109/DATE.2001.915002

Dücker, M., Geiger, C., Hunstock, R., Lehrenfeld, G., &; Müller, W. (1997). Visual-Textual Prototyping of 4D Scenes. Proceedings of the 1997 IEEE Symposium on Visual Languages. 1997 IEEE Symposium on Visual Languages.https://doi.org/10.1109/VL.1997.626601 
LibreCat: /record/39505
DOI: 10.1109/VL.1997.626601

Griebel, P., Lehrenfeld, G., Müller, W., Tahedl, C., &; Uhr, H. (1996). Integrating a Constraint Solver into a Real-Time Animation Environment. Proceedings of the 1996 IEEE Symposium on Visual Languages.https://doi.org/10.1109/VL.1996.545262 
LibreCat: /record/39521
DOI: 10.1109/VL.1996.545262