An Integrated Fuzzy Analytic Network Process and Fuzzy Regression Method for Bitcoin Price Prediction
A. Amiri, M. Tavana, H. Arman, Internet of Things 25 (2024).
LibreCat: /record/53213
DOI: 10.1016/j.iot.2023.101027

Data-driven simulation-based decision support system for resource allocation in industry 4.0 and smart manufacturing
E. Mahmoodi, M. Fathi, M. Tavana, M. Ghobakhloo, A.H.C. Ng, Journal of Manufacturing Systems 72 (2024) 287–307.
LibreCat: /record/53212
DOI: 10.1016/j.jmsy.2023.11.019

Breaking the exascale barrier for the electronic structure problem in ab-initio molecular dynamics
R. Schade, T. Kenter, H. Elgabarty, M. Lass, T. Kühne, C. Plessl, The International Journal of High Performance Computing Applications (2023).
LibreCat: /record/45361
DOI: 10.1177/10943420231177631

Workload-Aware Periodic Interconnect BIST
S. Sadeghi-Kohan, S. Hellebrand, H.-J. Wunderlich, IEEE Design &;Test (2023) 1–1.
LibreCat: /record/46264
DOI: 10.1109/mdat.2023.3298849

An interval multi-criteria decision-making model for evaluating blockchain-IoT technology in supply chain networks
M. Tavana, A. Khalili Nasr, A.B. Ahmadabadi, A.S. Amiri, H. Mina, Internet of Things 22 (2023).
LibreCat: /record/53220
DOI: 10.1016/j.iot.2023.100786

Hardware Trojans in Reconfigurable Computing
Q.A. Ahmed, Hardware Trojans in Reconfigurable Computing,  Paderborn University, Paderborn, Germany, Paderborn, 2022.
LibreCat: /record/29769
DOI: 10.17619/UNIPB/1-1271

A parameterized view on the complexity of dependence and independence logic
J. Kontinen, A. Meier, Y. Mahmood, Journal of Logic and Computation 32 (2022) 1624–1644.
LibreCat: /record/45847
DOI: 10.1093/logcom/exac070

Towards electronic structure-based ab-initio molecular dynamics simulations with hundreds of millions of atoms
R. Schade, T. Kenter, H. Elgabarty, M. Lass, O. Schütt, A. Lazzaro, H. Pabst, S. Mohr, J. Hutter, T. Kühne, C. Plessl, Parallel Computing 111 (2022).
LibreCat: /record/33684
DOI: 10.1016/j.parco.2022.102920

Guaranteeing Properties of Reconfigurable Hardware Circuits with Proof-Carrying Hardware
T. Wiersema, Guaranteeing Properties of Reconfigurable Hardware Circuits with Proof-Carrying Hardware, Paderborn University, Paderborn, 2021.
LibreCat: /record/26746

Exploiting Hardware-Based Data-Parallel and Multithreading Models for Smart Edge Computing in Reconfigurable FPGAs
A. Rodriguez, A. Otero, M. Platzner, E. De la Torre, IEEE Transactions on Computers (2021) 1–1.
LibreCat: /record/30907
DOI: 10.1109/tc.2021.3107196

Software/Hardware Co-Verification for Custom Instruction Set Processors
M.-C. Jakobs, F. Pauck, M. Platzner, H. Wehrheim, T. Wiersema, IEEE Access (2021).
LibreCat: /record/27841
DOI: 10.1109/ACCESS.2021.3131213

Proof-carrying Approximate Circuits
L.M. Witschen, T. Wiersema, M. Platzner, IEEE Transactions On Very Large Scale Integration Systems 28 (2020) 2084–2088.
LibreCat: /record/17358
DOI: 10.1109/TVLSI.2020.3008061

Parameterized complexity of abduction in Schaefer’s framework
Y. Mahmood, A. Meier, J. Schmidt, Journal of Logic and Computation 31 (2020) 266–296.
LibreCat: /record/45845
DOI: 10.1093/logcom/exaa079

Enforcing IP Core Connection Properties with Verifiable Security Monitors
F.P. Jentzsch, Enforcing IP Core Connection Properties with Verifiable Security Monitors, Universität Paderborn, 2018.
LibreCat: /record/1097

Evolvable caches: Optimization of reconfigurable cache mappings for a LEON3/Linux-based multi-core processor
N. Ho, P. Kaufmann, M. Platzner, in: 2017 International Conference on Field Programmable Technology (ICFPT), 2017, pp. 215–218.
LibreCat: /record/10676
DOI: 10.1109/FPT.2017.8280144

Computational self-awareness as design approach for visual sensor nodes
Z. Guettatfi, P. Hübner, M. Platzner, B. Rinner, in: 12th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC), 2017, pp. 1–8.
LibreCat: /record/10780
DOI: 10.1109/ReCoSoC.2017.8016147

FPGA-based acceleration of high density myoelectric signal processing
A. Boschmann, A. Agne, L.M. Witschen, G. Thombansen, F. Kraus, M. Platzner, in: 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2016.
LibreCat: /record/15873
DOI: 10.1109/reconfig.2015.7393312

Over effective hard real-time hardware tasks scheduling and allocation
Z. Guettatfi, O. Kermia, A. Khouas, in: 25th International Conference on Field Programmable Logic and Applications (FPL), Imperial College, 2015.
LibreCat: /record/10779
DOI: 10.1109/FPL.2015.7293994

Flexible Electronics: Integration Processes for Organic and Inorganic Semiconductor-Based Thin-Film Transistors
F. Vidor, T. Meyers, U. Hilleringmann, Electronics 4 (2015) 480–506.
LibreCat: /record/39479
DOI: 10.3390/electronics4030480

A hardware/software infrastructure for performance monitoring on LEON3 multicore platforms
N. Ho, P. Kaufmann, M. Platzner, in: 24th Intl. Conf. on Field Programmable Logic and Applications (FPL), 2014, pp. 1–4.
LibreCat: /record/10674
DOI: 10.1109/FPL.2014.6927437

A Scalable Formal Debugging Approach with Auto-Correction Capability based on Static Slicing and Dynamic Ranking for RTL Datapath Designs
B. Alizadeh, P. Behnam, S. Sadeghi-Kohan, IEEE Transactions on Computers (2014) 1–1.
LibreCat: /record/46266
DOI: 10.1109/tc.2014.2329687

Dynamic reliability management: Reconfiguring reliability-levels of hardware designs at runtime
J. Anwer, S. Meisner, M. Platzner, in: Reconfigurable Computing and FPGAs (ReConFig), 2013 International Conference On, 2013, pp. 1–6.
LibreCat: /record/10620
DOI: 10.1109/ReConFig.2013.6732280

Mutation-Analysis Driven Functional Verification of a Soft Microprocessor
T. Xie, W. Müller, F. Letombe, in: Proceedings of SO, IEEE,  Niagara Falls, NY, USA , 2012.
LibreCat: /record/36994
DOI: 10.1109/SOCC.2012.6398362

Assertion-Based Verification of RTOS Properties
M.F.S. Oliveira, H. Zabel, W. Müller, in: Proceedings of DATE’10, IEEE, Dresden, 2010.
LibreCat: /record/37009
DOI: 10.1109/DATE.2010.5457130

Timing Modeling and Analysis for AUTOSAR-Based Software Development - A Case Study
K. Klobedanz, C. Kuznik, A. Thuy, W. Müller, in: Proceedings of DATE’10, Dresden, IEEE, Dresden, 2010.
LibreCat: /record/37011
DOI: 10.1109/DATE.2010.5457125

RTOS-Aware Refinement for TLM2.0-based HW/SW Design
M. Becker, G. Di Guglielmo, F. Fummi, W. Müller, G. Pravadelli, T. Xie, in: Proceedings of DATE’10, IEEE, Dresden, 2010.
LibreCat: /record/37040
DOI: 10.1109/DATE.2010.5456965

Verification of Real-Time Properties for Hardware-Dependant Software
W. Müller, M.F. da S. Oliveira, H. Zabel, M. Becker, in: Proceedings of HLD, IEEE, 2010.
LibreCat: /record/37053

Hardware-dependent Software - Introduction and Overview
W. Ecker, W. Müller, R. Dömer, in: W. Ecker, W. Müller, R. Dömer (Eds.), Hardware Dependent Software - Principles and Practice, Springer Verlag, Dordrecht, 2009, pp. 1–14.
LibreCat: /record/33814
DOI: 10.1007/978-1-4020-9436-1_1

EvoCaches: Application-specific Adaptation of Cache Mapping
P. Kaufmann, C. Plessl, M. Platzner, in: Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS), IEEE Computer Society, Los Alamitos, CA, USA, 2009, pp. 11–18.
LibreCat: /record/2262

MOVES: A Modular Framework for Hardware Evolution
P. Kaufmann, M. Platzner, in: Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), IEEE, 2007, pp. 447–454.
LibreCat: /record/6508
DOI: 10.1109/ahs.2007.73

Server-based execution of periodic tasks on dynamically reconfigurable hardware
K. Danne, R. Mühlenbernd, M. Platzner, IET Computers Digital Techniques 1 (2007) 295–302.
LibreCat: /record/10646
DOI: 10.1049/iet-cdt:20060186

A Formal Behavioral Semantics for TestML
J. Großmann, W. Müller, in: Proc. of ISOLA 06, Paphos, Cyprus, 2006.
LibreCat: /record/38107
DOI: 10.1109/ISoLA.2006.37

A Model-Based Approach for Executable Specification on Reconfigurable Hardware
T. Schattkowsky, W. Müller, A. Rettberg, in: Proceedings of DATE’05, IEEE, Munich, Germany , 2005.
LibreCat: /record/39029
DOI: 10.1109/DATE.2005.20

A UML Virtual Machine for Embedded Systems
T. Schattkowsky, W. Müller, in: Proceedings of ISNG 05, Las Vegas, NV, 2005.
LibreCat: /record/39030

Transformation of UML State Machines for Direct Execution
T. Schattkowsky, W. Müller, in: Proceedings of VL/HCC 05, Dallas, TX, USA, 2005.
LibreCat: /record/39032
DOI: 10.1109/VLHCC.2005.64

Virtualization of Hardware – Introduction and Survey
C. Plessl, M. Platzner, in: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2004, pp. 63–69.
LibreCat: /record/2415

VLSI technologies for artificial neural networks
K. Goser, U. Hilleringmann, U. Rueckert, K. Schumacher, IEEE Micro 9 (2002) 28–44.
LibreCat: /record/39925
DOI: 10.1109/40.42985

VLSI technologies for artificial neural networks
K. Goser, U. Hilleringmann, U. Rueckert, K. Schumacher, IEEE Micro 9 (2002) 28–44.
LibreCat: /record/39926
DOI: 10.1109/40.42985

The Simulation Semantics of SystemC
W. Müller, J. Ruf, D.W. Hoffmann, J. Gerlach, T. Kropf, W. Rosenstiehl, in: Proceedings of the Design, Automation, and Test in Europe (DATE’01), IEEE, Munich, Germany , 2001.
LibreCat: /record/39421
DOI: 10.1109/DATE.2001.915002

Visual-Textual Prototyping of 4D Scenes
M. Dücker, C. Geiger, R. Hunstock, G. Lehrenfeld, W. Müller, in: Proceedings of the 1997 IEEE Symposium on Visual Languages, Capri, Italy, 1997.
LibreCat: /record/39505
DOI: 10.1109/VL.1997.626601

Integrating a Constraint Solver into a Real-Time Animation Environment
P. Griebel, G. Lehrenfeld, W. Müller, C. Tahedl, H. Uhr, in: Proceedings of the 1996 IEEE Symposium on Visual Languages, Boulder CO, 1996.
LibreCat: /record/39521
DOI: 10.1109/VL.1996.545262