Jakobs, M.-C., Pauck, F., Platzner, M., Wehrheim, H., &; Wiersema, T. (2021). Software/Hardware Co-Verification for Custom Instruction Set Processors. IEEE Access.https://doi.org/10.1109/ACCESS.2021.3131213 
LibreCat: /record/27841
DOI: 10.1109/ACCESS.2021.3131213

Witschen, L. M., Wiersema, T., &; Platzner, M. (2020). Proof-carrying Approximate Circuits. IEEE Transactions On Very Large Scale Integration Systems, 28(9), 2084–2088.https://doi.org/10.1109/TVLSI.2020.3008061 
LibreCat: /record/17358
DOI: 10.1109/TVLSI.2020.3008061

Mahmood, Y., Meier, A., &; Schmidt, J. (2020). Parameterized complexity of abduction in Schaefer’s framework. Journal of Logic and Computation, 31(1), 266–296.https://doi.org/10.1093/logcom/exaa079 
LibreCat: /record/45845
DOI: 10.1093/logcom/exaa079

Jentzsch, F. P. (2018). Enforcing IP Core Connection Properties with Verifiable Security Monitors. Universität Paderborn.
LibreCat: /record/1097

Ho, N., Kaufmann, P., &; Platzner, M. (2017). Evolvable caches: Optimization of reconfigurable cache mappings for a LEON3/Linux-based multi-core processor. In 2017 International Conference on Field Programmable Technology (ICFPT) (pp. 215–218).https://doi.org/10.1109/FPT.2017.8280144 
LibreCat: /record/10676
DOI: 10.1109/FPT.2017.8280144

Guettatfi, Z., Hübner, P., Platzner, M., &; Rinner, B. (2017). Computational self-awareness as design approach for visual sensor nodes. In 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC) (pp. 1–8).https://doi.org/10.1109/ReCoSoC.2017.8016147 
LibreCat: /record/10780
DOI: 10.1109/ReCoSoC.2017.8016147

Boschmann, A., Agne, A., Witschen, L. M., Thombansen, G., Kraus, F., &; Platzner, M. (2016). FPGA-based acceleration of high density myoelectric signal processing. In 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig). Mexiko City, Mexiko: IEEE.https://doi.org/10.1109/reconfig.2015.7393312 
LibreCat: /record/15873
DOI: 10.1109/reconfig.2015.7393312

Guettatfi, Z., Kermia, O., &; Khouas, A. (2015). Over effective hard real-time hardware tasks scheduling and allocation. In 25th International Conference on Field Programmable Logic and Applications (FPL). Imperial College.https://doi.org/10.1109/FPL.2015.7293994 
LibreCat: /record/10779
DOI: 10.1109/FPL.2015.7293994

Vidor, F., Meyers, T., &; Hilleringmann, U. (2015). Flexible Electronics: Integration Processes for Organic and Inorganic Semiconductor-Based Thin-Film Transistors. Electronics, 4(3), 480–506.https://doi.org/10.3390/electronics4030480 
LibreCat: /record/39479
DOI: 10.3390/electronics4030480

Ho, N., Kaufmann, P., &; Platzner, M. (2014). A hardware/software infrastructure for performance monitoring on LEON3 multicore platforms. In 24th Intl. Conf. on Field Programmable Logic and Applications (FPL) (pp. 1–4).https://doi.org/10.1109/FPL.2014.6927437 
LibreCat: /record/10674
DOI: 10.1109/FPL.2014.6927437

Alizadeh, B., Behnam, P., &; Sadeghi-Kohan, S. (2014). A Scalable Formal Debugging Approach with Auto-Correction Capability based on Static Slicing and Dynamic Ranking for RTL Datapath Designs. IEEE Transactions on Computers, 1–1.https://doi.org/10.1109/tc.2014.2329687 
LibreCat: /record/46266
DOI: 10.1109/tc.2014.2329687

Anwer, J., Meisner, S., &; Platzner, M. (2013). Dynamic reliability management: Reconfiguring reliability-levels of hardware designs at runtime. In Reconfigurable Computing and FPGAs (ReConFig), 2013 International Conference on (pp. 1–6).https://doi.org/10.1109/ReConFig.2013.6732280 
LibreCat: /record/10620
DOI: 10.1109/ReConFig.2013.6732280

Xie, T., Müller, W., &; Letombe, F. (2012). Mutation-Analysis Driven Functional Verification of a Soft Microprocessor. Proceedings of SO.https://doi.org/10.1109/SOCC.2012.6398362 
LibreCat: /record/36994
DOI: 10.1109/SOCC.2012.6398362

Oliveira, M. F. S., Zabel, H., &; Müller, W. (2010). Assertion-Based Verification of RTOS Properties. Proceedings of DATE’10. 2010 Design, Automation &; Test in Europe Conference &; Exhibition (DATE 2010), Dresden.https://doi.org/10.1109/DATE.2010.5457130 
LibreCat: /record/37009
DOI: 10.1109/DATE.2010.5457130

Klobedanz, K., Kuznik, C., Thuy, A., &; Müller, W. (2010). Timing Modeling and Analysis for AUTOSAR-Based Software Development - A Case Study. Proceedings of DATE’10, Dresden. 2010 Design, Automation &; Test in Europe Conference &; Exhibition (DATE 2010), Dresden.https://doi.org/10.1109/DATE.2010.5457125 
LibreCat: /record/37011
DOI: 10.1109/DATE.2010.5457125

Becker, M., Di Guglielmo, G., Fummi, F., Müller, W., Pravadelli, G., &; Xie, T. (2010). RTOS-Aware Refinement for TLM2.0-based HW/SW Design. Proceedings of DATE’10. Design, Automation &; Test in Europe Conference &; Exhibition (DATE 2010), Dresden.https://doi.org/10.1109/DATE.2010.5456965 
LibreCat: /record/37040
DOI: 10.1109/DATE.2010.5456965

Müller, W., da S. Oliveira, M. F., Zabel, H., &; Becker, M. (2010). Verification of Real-Time Properties for Hardware-Dependant Software. Proceedings of HLD. IEEE International High Level Design Validation and Test Workshop (HLDVT), Anaheim, FL, USA.
LibreCat: /record/37053

Ecker, W., Müller, W., &; Dömer, R. (2009). Hardware-dependent Software - Introduction and Overview. In W. Ecker, W. Müller, &; R. Dömer (Eds.), Hardware Dependent Software - Principles and Practice (pp. 1–14). Springer Verlag.https://doi.org/10.1007/978-1-4020-9436-1_1 
LibreCat: /record/33814
DOI: 10.1007/978-1-4020-9436-1_1

Kaufmann, P., Plessl, C., &; Platzner, M. (2009). EvoCaches: Application-specific Adaptation of Cache Mapping. Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS), 11–18.
LibreCat: /record/2262

Kaufmann, P., &; Platzner, M. (2007). MOVES: A Modular Framework for Hardware Evolution. In Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007) (pp. 447–454). Edinburgh, UK: IEEE.https://doi.org/10.1109/ahs.2007.73 
LibreCat: /record/6508
DOI: 10.1109/ahs.2007.73