Redesigning the TETRISC Architecture for Scalable Rocket Chip Implementations
K.A. Hannemann, L. Luchterhandt, W. Müller, M. Ulbricht, L. Lu, in: 38. ITG / GMM / GI - Workshop Testmethoden Und Zuverlässigkeit von Schaltungen Und Systemen, Potsdam, 2026.

Evolvable caches: Optimization of reconfigurable cache mappings for a LEON3/Linux-based multi-core processor
N. Ho, P. Kaufmann, M. Platzner, in: 2017 International Conference on Field Programmable Technology (ICFPT), 2017, pp. 215–218.

Computational self-awareness as design approach for visual sensor nodes
Z. Guettatfi, P. Hübner, M. Platzner, B. Rinner, in: 12th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC), 2017, pp. 1–8.

Microarchitectural optimization by means of reconfigurable and evolvable cache mappings
N. Ho, A.F. Ahmed, P. Kaufmann, M. Platzner, in: Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS), 2015, pp. 1–7.

A hardware/software infrastructure for performance monitoring on LEON3 multicore platforms
N. Ho, P. Kaufmann, M. Platzner, in: 24th Intl. Conf. on Field Programmable Logic and Applications (FPL), 2014, pp. 1–4.

Towards self-adaptive caches: A run-time reconfigurable multi-core infrastructure
N. Ho, P. Kaufmann, M. Platzner, in: 2014 IEEE Intl. Conf. on Evolvable Systems (ICES), 2014, pp. 31–37.