Can Tax Rate Changes Accelerate Investment under Entry and Exit Flexibility? – Insights from an Economic Experiment
R. Fahr, E.A. Janssen, C. Sureth-Sloane, FinanzArchiv / European Journal of Public Finance 78 (2022) 239–289.

Approaches for Collaborative Security Defences in Multi Network Environments
R. Koning, G. Polevoy, L. Meijer, C. de Laat, P. Grosso, in: 2019 6th IEEE International Conference on Cyber Security and Cloud Computing (CSCloud)/ 2019 5th IEEE International Conference on Edge Computing and Scalable Cloud (EdgeCom), 2019, pp. 113–123.

Assertion-Based Verification of RTOS Properties
M.F.S. Oliveira, H. Zabel, W. Müller, in: Proceedings of DATE’10, IEEE, Dresden, 2010.

Timing Modeling and Analysis for AUTOSAR-Based Software Development - A Case Study
K. Klobedanz, C. Kuznik, A. Thuy, W. Müller, in: Proceedings of DATE’10, Dresden, IEEE, Dresden, 2010.

RTOS-Aware Refinement for TLM2.0-based HW/SW Design
M. Becker, G. Di Guglielmo, F. Fummi, W. Müller, G. Pravadelli, T. Xie, in: Proceedings of DATE’10, IEEE, Dresden, 2010.

Verification of Real-Time Properties for Hardware-Dependant Software
W. Müller, M.F. da S. Oliveira, H. Zabel, M. Becker, in: Proceedings of HLD, IEEE, 2010.

RTOS-Aware Refinement for TLM2.0-based HW/SW Design
M. Becker, G. Di Guglielmo, F. Fummi, W. Müller, G. Pravadelli, T. Xie, in: Proceedings of DATE’10, IEEE, Dresden, 2010.

Increased Accuracy through Noise Injection in Abstract RTOS Simulation
H. Zabel, W. Müller, in: Proceedings of DATE’09, Nice, France, 2009.

A Generic System for Interactive Real--Time Animation
M. Dücker, G. Lehrenfeld, W. Müller, C. Tahedl, in:  Proceedings International Conference and Workshop on Engineering of Computer-Based Systems, Monterey, CA, USA , 1997.

Transforming SDL Diagrams Into a Complete Visual Representation
G. Lehrenfeld, W. Müller, C. Tahedl, in: Proceedings of Symposium on Visual Languages,  Darmstadt, Germany , 1995.

Complete Visual Specification and Animations of Protocols
W. Müller, G. Lehrenfeld, C. Tahedl, in: Proceedings of ASP-DAC’95/CHDL’95/VLSI’95 with EDA Technofair, Chiba, Japan , 1995.