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Jentzsch FP. Enforcing IP Core Connection Properties with Verifiable Security Monitors. Universität Paderborn; 2018.
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Kuznik C, Müller W, Defo GB. An Assisted Single Source Verification Metric Model Code Generation Methodology. In: ; 2014.
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Koppelmann B, Messidat B, Becker M, Müller W, Scheytt JC. Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU. In: Proceedings of the Design and Verification Conference Europe (DVCON Europe). ; 2014.
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Woehrle M, Plessl C, Lim R, Beutel J, Thiele L. EvAnT: Analysis and Checking of event traces for Wireless Sensor Networks. In: IEEE Int. Conf. on Sensor Networks, Ubiquitous, and Trustworthy Computing (SUTC). IEEE Computer Society; 2008:201-208. doi:10.1109/SUTC.2008.24
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Flake S, Müller W. Past- and Future-Oriented Time-Bound Temporal Properties with OCL. In: Proceedings of SEFM´04. IEEE; 2004. doi:10.1109/SEFM.2004.1347516
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Müller W, Dömer R, Gerstlauer A. The Formal Execution Semantics of SpecC. In: Proceedings of the ISS. ; 2002. doi:10.1145/581199.581234 
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Flake S, Müller W. Specification of Real-Time Properties for UML Models. In: Proceedings of HICSS-35. ; 2002. doi:10.1109/HICSS.2002.994469
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Müller W, Ruf J, Hoffmann DW, Gerlach J, Kropf T, Rosenstiehl W. The Simulation Semantics of SystemC. In: Proceedings of the Design, Automation, and Test in Europe (DATE’01). IEEE; 2001. doi:10.1109/DATE.2001.915002
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Börger E, Glässer U, Müller W. A Formal Definition of an Abstract VHDL’93 Simulator by EA-Machines. In: Delgado Kloos C, Breuer PT, eds. Semantics of VHDL. Kluwer Academic Publishers; 1995:107-139. doi:10.1007/978-1-4615-2237-9_5
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